Comments (10)
from riscv-isa-sim.
Thank you for your reply! But I didn't get it why setting xPIE=1 can be used to detect software bugs. So it seems that we can treat the spec as saying xPIE can be anything after executing xRET, correct?
from riscv-isa-sim.
If a SRET is followed by a non-delegated trap into M-mode, the M-mode code can observe the value of SPIE which was written by SRET.
from riscv-isa-sim.
By "benign" I meant it doesn't create a security hole. It's still a bug and Spike needs to be fixed. I'll do so shortly.
from riscv-isa-sim.
Thank you very much for your reply!
Sorry for bothering you again, but I just have one more question. It seems legal to execute an SRET instruction when in M-mode. Is this behavior desired?
from riscv-isa-sim.
It is legal. In practice, it is not likely to be especially useful, but allowing all instructions in M-mode simplifies testing.
from riscv-isa-sim.
Hi Andrew,
It is legal to execute sret in M mode only if S mode is available right?
If S mode is not supported, isn't sret illegal?
from riscv-isa-sim.
That’s right.
from riscv-isa-sim.
from riscv-isa-sim.
Spike doesn't support configuring which privilege modes are available (yet).
from riscv-isa-sim.
Related Issues (20)
- `fdiv.s` with a dynamic rounding mode set to `REN` on the spike results in a incorrect rounding HOT 1
- `fmv.w.x` is illegal? HOT 6
- Bug Fix Suggestion for v1.1.0 HOT 1
- Installation Guide for v1.1.0
- SPIKE + PK C++ `iostream` support HOT 2
- Wrong mstatus.[SXL|UXL] for RV64I in M-mode only config HOT 4
- RV32E - exception priority issue HOT 1
- Discrepancy with respect to maskmax field in mcontrol (spec vs spike) HOT 3
- trap instruction page fault error and mode shifting from M-mode to U-mode in spike debug mode
- Logging the value of registers at a certain point during the simulation possible? HOT 1
- RISC-V Standard Spec Trace Support
- VI_LD_INDEX issue HOT 3
- SFENCE.VMA instruction privilege HOT 1
- Ssdbltrp - VS mode double trap check HOT 4
- Building spike with "--with-priv=m" config option renders spike unusable HOT 13
- Default `pmpcfg0 = 0x000000000000001f` and `pmpaddr0 = 0x003fffffffffffff`. HOT 5
- Smdbltrp - VS mode double trap check HOT 2
- Using RISCV FESVR for lockstep verif in C HOT 3
- Clarification on VMSEQ Instruction Behavior (riscv vector spec1.0) HOT 1
- How to forcefully inject the rtl values into spike HOT 1
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from riscv-isa-sim.