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rickkas7 avatar rickkas7 commented on August 23, 2024

I have no idea why that's not working. writeRegister must be working, as it's used all over the place to set every other registers. The write bit part is handled within Device OS, which is why you don't see code for it, but it is handled.

Page 21 clearly says you need to set the LCR to 0xBF. However it's quite possible that once you've set the LCR to 0xBF that reading register 0x3 (LCR) will instead attempt to return extended register 0x3, which doesn't exist. Who knows what problems that might cause. But it would explain why you don't get 0xBF back.

I think there might be a bug in the begin method. After setting the special register set with LCR=0x80, it exits special register mode by settings LCR to 0xBF. I think that's wrong. It should probably save and restore the LCR because it looks like the enhanced register set will be set and setting the FCR_IIR_REG in begin will fail.

I'd try:

  • Fix begin() to save and restore LCR
  • Read the LCR before you set it to see what it is
  • Remove the call to read the LCR after setting it because that might be causing problems by itself

from sc16is740rk.

CaptainMack avatar CaptainMack commented on August 23, 2024

Thanks, I'll try it out in a couple of hours and update here!

from sc16is740rk.

CaptainMack avatar CaptainMack commented on August 23, 2024

I've tried making the modifications as you mentioned - the begin-function is now as follows:

   bool SC16IS740Base::begin(int baudRate, uint8_t options) {
preBegin();

// My test board uses this oscillator
// KC3225K1.84320C1GE00
// OSC XO 1.8432MHz CMOS SMD $1.36
// https://www.digikey.com/product-detail/en/avx-corp-kyocera-corp/KC3225K1.84320C1GE00/1253-1488-1-ND/5322590
// Another suggested frequency from the data sheet is 3.072 MHz

// The divider devices the clock frequency to 16x the baud rate
int div = oscillatorHz / (baudRate * 16);

// Read Status
readRegister(LCR_REG); // returns 0 on startup

// Set Enhanced Function Bit first
writeRegister(LCR_REG, EFR_REGISTER_START); // Set to LCR 0xbf to enable access to EFR register
writeRegister(EFR_REG, EFR_ENHANCED_BIT); // Set 4th bit to 1 (0x10) to enable enhanced functions.
writeRegister(LCR_REG, LCR_SPECIAL_END); // Set LCR to 0x00 as originally read.
writeRegister(IEF_REG, EFR_ENHANCED_BIT); // Set 4th bit to 1 (0x10) to enable sleep mode

writeRegister(LCR_REG, LCR_SPECIAL_START); // 0x80 
writeRegister(DLL_REG, div & 0xff);
writeRegister(DLH_REG, div >> 8);
writeRegister(LCR_REG, LCR_SPECIAL_END); // 0x00


writeRegister(LCR_REG, options & 0x3f);

// Enable FIFOs
writeRegister(FCR_IIR_REG, 0x07); // Enable FIFO, Clear RX and TX FIFOs

// Also MCR?
return true;
   }

Which in turn gives me following print out:

0000010331 [dryp.extser] TRACE: readRegister reg=3 value=0 // LCR is 0 from the get-go
0000010331 [dryp.extser] TRACE: writeRegister reg=3 value=191 stat=0 // Write 0xbf to LCR
0000010332 [dryp.extser] TRACE: writeRegister reg=2 value=16 stat=3  // Write 0x10 to EFR, timeout on address? 
0000010333 [dryp.extser] TRACE: writeRegister reg=3 value=0 stat=0  // Write 0 to LCR as originally read
0000010333 [dryp.extser] TRACE: writeRegister reg=1 value=16 stat=0  // Write 0x10 to IEF/IER REG (sleep mode bit), works? But should only work if EFR bit has been set, which seems like it fails?

0000010334 [dryp.extser] TRACE: writeRegister reg=3 value=128 stat=0 // Write 0x80 to LCR
0000010335 [dryp.extser] TRACE: writeRegister reg=0 value=12 stat=0  // Write to DLL reg
0000010335 [dryp.extser] TRACE: writeRegister reg=1 value=0 stat=0  // Write to DLH reg
0000010336 [dryp.extser] TRACE: writeRegister reg=3 value=0 stat=0   // Write 0x00 to LCR reg as originally read
0000010336 [dryp.extser] TRACE: writeRegister reg=3 value=3 stat=0 // Write options to LCR reg
0000010337 [dryp.extser] TRACE: writeRegister reg=2 value=7 stat=3 // Write 0x07 to FCR_IIR_REG, but fails?

It seems like the EFR register (subaddress 0x03) and FCR_IIR register (subaddress 0x02) fails with error code 3, alas end of address transmission timeout.

Looking at the logic analyzer on those two specific transmissions, I see following that it fails/NACKs on the data package being sent (the subaddress).
EFR register:
name type start_time duration data ack address read
I2C address 52.1839174 2.17e-05 true 0x48 false
I2C data 52.183943 2.1675e-05 0x10 false

FCR_IIR register:

name type start_time duration data ack address read
I2C address 52.189231 2.17e-05 true 0x48 false
I2C data 52.1892566 2.1675e-05 0x10 false

The weird thing is the 0x10 on both subaddresses? The EFR address is 0x02 and the FCR_IIR address is 0x02 shifted 3 times left becomes 0x10 - why does it fail for this specific address both in the general registers and the enhanced function registers? LCR is used to switch between the two, but it doesn't seem to have any effect. I'm a bit confused by what is happening.

i2c

from sc16is740rk.

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