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apollo

An open autonomous driving platform

blog.dcrclub.org

dcrclub articles

chisel-book

Hardware design with Chisel

chisel3

Chisel 3: A Modern Hardware Design Language

cnrv-fpu

Basic floating-point components for RISC-V processors

dcrdex

The Decred Decentralized Exchange (DEX), powered by atomic-swaps.

dcrdocs

Documentation for Decred.

decred_lx9

Decred FPGA Miner Demo For Spartan LX9 Chip

firemarshal

Automatically Builds a Linux Distribution for FireSim/FireChip Nodes, works with FireSim's automatic workload generation.

gpgpu-sim_distribution

GPGPU-Sim provides a detailed simulation model of contemporary NVIDIA GPUs running CUDA and/or OpenCL workloads. It includes support for features such as TensorCores and CUDA Dynamic Parallelism as well as a performance visualization tool, AerialVisoin, and an integrated energy model, GPUWattch.

h265-encoder-rtl

hw

RTL, Cmodel, and testbench for NVDLA

incubator-tvm

Open deep learning compiler stack for cpu, gpu and specialized accelerators

nvgen

NVDLA generator, aiming to optimize the design agility and hardware performance.

nvidia-dla-blocks

pyspice

Simulate electronic circuit using Python and the Ngspice / Xyce simulators

riscv-linux

sodla

soDLA ownership has been transfered to soDLA-publishment. This repo is to torture soDLA.

sodla_dev

development mode of soDLA

sodla_doc

This is the documentation for soDLA project.

sodla_equi

equivalence checking for soDLA

sw

NVDLA SW

udacity_carnd_term1

Some reference solution for carnd term1

udacity_dlnd

Reference solution for udacity deep learning nanodegree foundations

xiangshan-chipyard

my solution of integrating xiangshan IP into chipyard