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CAN Protocol Controller
An CAN bus Controller implemented in Verilog
- Designed the LDPC decoder in the Matlab using the min-sum approach. - Designed quantized RTL in Verilog with the min-sum approach and parallel architecture. - Created modules for all variants of the variable node unit(VNU) and the check-node unit(CNU) based on the H matrix. Created script for module instantiation of VNU and CNU as per the H matrix. - Verified the functionality of the Verilog implementation by self-checking test-bench in Verilog to compare the results with Matlab.
DVB-S2 LDPC Decoder
The Ultra-Low Power RISC Core
RTL, Cmodel, and testbench for NVDLA
C and MATLAB implementation for LDPC encoding and decoding
Software for Low Density Parity Check codes
Low Density Parity Check Decoder
RISC-V Linux Port
configurable cordic core in verilog
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