Name: Francisco Javier Reina Campo
Type: User
Company: QueenField
Bio: I am an Electronic Engineer specialized in digital design and verification, with emphasis on Hardware Description Languages ((System)Verilog, VHDL).
Location: Abu Dhabi
Blog: http://queenfield.tech
Francisco Javier Reina Campo's Projects
Distribution for RTOS
Operating System for RTOS
Kernel for RTOS
Kernel Interface Generator for RTOS
Debugger on Chip for MPSoC
Direct Access Memory for MPSoC
Digital Signature Algorithm for MPSoC
Multi-Processor System on Chip verified with UVM/OSVVM/FV
Financial Technology with MPSoC-NTM verified with UVM/OSVVM/FV
General Purpose Input Output for MPSoC
Message Passing Interface for MPSoC
Multi-Port RAM for Instruction & Data for MPSoC
Master Slave Interface for MPSoC
Multi-Processor System on Chip with MSP430-16
Network on Chip for MPSoC
Neural Turing Machine for a Multi-Processor System on Chip verified with UVM/OSVVM/FV
Multi-Processor System on Chip with OpenRISC-32 / OpenRISC-64
Multi-Processor System on Chip with RISCV-32 / RISCV-64 / RISCV-128
Distribution for a MPSoC
Single-Port RAM for Instruction & Data for MPSoC
Universal Asynchronous Receiver-Transmitter for MPSoC
GNU toolchain for MSP430
Open Neural Network
Binutils and GDB for OpenRISC
GCC for OpenRISC
GNU toolchain for OpenRISC
Newlib for OpenRISC
Open Source VHDL Verification Methodology
Processing Unit verified with UVM/OSVVM/FV
Financial Technology with PU-NTM verified with UVM/OSVVM/FV