NONCOMP clears the result bit for signaling NaNs in "not equal" compare about cvfpu HOT 1 CLOSED

According to the base RISC-V FP specification, the result of any comparison instruction involving NaN is 0. Furthermore, the invalid flag is raised for all NaN operands to LT and LE, and for signalling NaN operands to EQ:

As such, the present implementation is correct for scalar implementations as the use of the operation modifier does not directly map to any RISC-V base-ISA FP instructions - which is why it wasn't documented.

For the V extension, the vfne instruction is defined and indeed behaves as you outline:

I was confused at first since you didn't explicitly mention the V-spec behavior, but your fix is in line with that and doesn't impact scalar implementations. LGTM.

from cvfpu.