Comments (1)
I change the virtual machine from ubuntu 18 to ubuntu 16, then the problem is solved... ...
from cv32e40p.
Related Issues (20)
- Implementation HOT 1
- PULP extend instructions encoding in cv32e40p_v1.2.1 User Manual HOT 1
- Does Prefetch Buffer's localparam FIFO_DEPTH and LSU's localparam DEPTH configurable? HOT 2
- Different bahavior between vsim and verilator for mcycle csr HOT 6
- Did Post-Incrementing Load & Store Instructions and Register-Register Load & Store Instructions support misalign load or store HOT 1
- Where is Pulp_Clocking_Gating file? HOT 3
- Is there any physical synthesis performed using 5nm technology for cv32e40p ? HOT 1
- HWLoops lpstart/lpend CSRs 2 LSBs can be written to any value. HOT 1
- genus reports referenced package cv32e40p_fpu_pkg does not exist HOT 2
- For xpulp SIMD ALU shift instructions with SCI mode CV.SRL.SCI, CV.SRA.SCI, CV.SLL.SCI 6-bit Imm usage ambiguity between User Manual and RTL HOT 1
- xpulp SIMD ALU instruction - CV.AVGU.SCI 6-bit Immidiate should be zero extended in the User Manual HOT 4
- The encoding table for the bit manipulation extension is not rendered HOT 3
- add LEC script for Siemens
- What is the current status of the standard? HOT 7
- XPULP SIMD Bit manipulation Instructions: cv.extract{u}.h/b, cv.insert.h/b 6-bit Imm6 ambiguity resolution for signed/unsigned notation HOT 1
- Naming of cv.slet HOT 3
- pulp hwloop count not decrementing to 0 after the end of hwloop body execution HOT 3
- Link to readthedocs on landing page no longer works HOT 3
- fix mimpid HOT 2
- Wrong Hierarchical Wiring in cv32e40p_tb_subsystem.sv Line **157** HOT 4
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