Comments (2)
Description
就比如 SD 的 controlnet,我们修改 pipeline 使当 conditioning_scale 为 0 时,使 down_block_res_samples 和 mid_block_res_sample 为 None,这样会导致 unet 的输入数量改变而重新编译静态图,请问有办法不重编么
这个是两种情况。 1. 这个可以理解为 conditioning_scale 为0 代表不使用 controlnet (可以将controlnet 模块删掉),2. conditioning_scale >0 代表使用 controlnet 。
@songh11 在 1 和 2 这两种情况切换是需要改变静态图。 防止 重编 可以提前缓存图参考 onediff: https://github.com/siliconflow/onediff/blob/main/onediff_diffusers_extensions/examples/pipe_compile_save_load.py
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Description
就比如 SD 的 controlnet,我们修改 pipeline 使当 conditioning_scale 为 0 时,使 down_block_res_samples 和 mid_block_res_sample 为 None,这样会导致 unet 的输入数量改变而重新编译静态图,请问有办法不重编么
这个是两种情况。 1. 这个可以理解为 conditioning_scale 为0 代表不使用 controlnet (可以将controlnet 模块删掉),2. conditioning_scale >0 代表使用 controlnet 。
@songh11 在 1 和 2 这两种情况切换是需要改变静态图。 防止 重编 可以提前缓存图参考 onediff: https://github.com/siliconflow/onediff/blob/main/onediff_diffusers_extensions/examples/pipe_compile_save_load.py
感谢回复
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