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cellprofileseperationbymatlab

This Project includes the several Image Process and Machine Learning Methodto seperate the different types of cell from a microscope image.

coremark

CoreMark® is an industry-standard benchmark that measures the performance of central processing units (CPU) and embedded microcrontrollers (MCU).

customrisc-v_llvm_backend

This is a simple tutorial to show LLVM-Backend Steps.

cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

darkarduinotheme

A dark theme for the Arduino IDE – no longer maintained :(

fingerpen-mouse

This project includes the IMU based mouse design, code, and related documents to draw in computer easily.

ghidra

Ghidra is a software reverse engineering (SRE) framework

greenrio2

hammer

Infrastructure to drive Spike (RISC-V ISA Simulator) in cosim mode. Hammer provides a C++ and Python interface to interact with Spike.

i2cdevlib

I2C device library collection for AVR/Arduino or other C++-based MCUs

mipsbasedsimplecpu

This work is just to understand to design of a cpu. It has single cycle 16-bit MiPS based architecture.

omerguzelelectronicguy

Config files for my GitHub profile.

openpiton

The OpenPiton Platform

riscv-coremark

Setup scripts and files needed to compile CoreMark on RISC-V

riscv-isa-sim

Spike, a RISC-V ISA Simulator

riscv-tests

vortex

yingmanwumen