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accelerated-android-vision

This project implements a mobile phone based traffic sign detection and recognition system assisted by a Convolutional Neural Network (CNN). Adequate effort is made to utilize heterogeneous computing as much as possible through the newly released Android Neural Networks API which intelligently distribute computationally intensive Neural Networks (NN) tasks to any available onboard accelerator (GPU/NN Accelerator).

armmbed-temperature-logger

This code is written to run on the ARMmbed LPC1768 board. It is developed to configure the board which is connected to a TMP102 to constantly measure temperature, update the display evey minute and also plot these values over time on the LCD

circlepointcalculator

clearcl

Multi-backend Java Object Oriented Facade API for OpenCL.

computer_vision_using_tensorflowlite

On this project, AlexNet Convolution Neural Network is trained using traffic sign images from the German Road Traffic Sign Benchmark. The initially trained network is then quantized and optimized for deployment on mobile devices using TensorFlow Lite

cracking-the-coding-interview-6th-edition

Personal Java solutions to questions in Gayle McDowell's Cracking the Coding Interview book (6th edition) and some other algorithm/data structure questions from GeeksforGeeks dot org

deep-learning-assisted-computer-vision-system

In summary, this project seeks to explore the science behind Neural Networks (NN), its various flavours, application areas and then finally, narrow down by applying it in the design and development of a computer vision system which can be used for traffic sign recognition and detection in autonomous vehicles. The project starts off by designing, developing, implementing and testing a model of the proposed vision system on a CPU using MATLAB and then afterwards, the performance of the implemented vision system is further optimized through vectorization, parallelism, legacy coding and heterogeneous computing. The project is concluded with detailed analysis and evaluation of the various optimization schemes utilized as well as an evaluation of the excellent Neural Network’s classification accuracy.

des_encryption_system

Encrypts streams of input bits based on the Data Encryption Standard (DES)

green-bridge-cbt

A computer based testing system

host-based-intrusion-detection-system-using-genetic-algorithm

The GA-IDS is a full-fledged host based intrusion detection system developed using the Java programming language to help detect packets having spoofed IP addresses. It first and foremost sniffs the incoming packets on the host system and there after analyzes them in order to detect an intrusion. Considering the fact that this sniffing process is a low level operation, the java application makes use of the Java Packet Capturing Library (JpCap) which works in conjunction with the Windows Packet Capturing Library (WinpCap).

jpeg_image_compressor

Split images into series of 8-by-8 matrix, performs DCT, quantize, normalizes and displays back compressed image

mini_component_toolbox_app

R-Toolbox is a resistor value calculator which contains 3 other vital Electronic Engineering tools. It is designed for three major purposes which are: 1. To serve as a quick tool that can be used to generate resistor values from their colour codes during lab experiments. 2. To serve as a quick tool that can be used to generate tantalum capacitor values from their colour codes during lab experiments. 3. To help perform spectral analysis of sine, cosine and square wave signals It was built using Java 8.0 on the NetBeans IDE platform

nbit_hardware_multiplier_and_test_bench

NBit hardware multiplier and test bench designed using Verilog Hardware Description Language. Multiplier is able to carry out multiplication of any n by n bit set of binary number.

recompose

recompose is a tool for converting Android layouts in XML to Kotlin code using Jetpack Compose.

rsa_encryption_and_decryption_module

RSA Encryption/Decryption module written on MATLAB

selenium

A browser automation framework and ecosystem.

verilog_three_lane_junction_traffic_control_simulator

This project holistically shows a case application of Field Programmable Gates Arrays (FPGAs) in the design of a 3-Lane Left-Hand Drive Cross Junction Traffic Control Simulator with Pedestrian Crossing Allowance. As a visual means of verifying the implemented system, a complete graphics driver is developed to show the real-time movement of the cars in response to the traffic controller states in the system. The hardware circuit and graphics operations are modelled on the FPGA using a textural Hardware Description Language (Verilog HDL) on Quartus II Integrated Development Environment (IDE) and ported to the FPGA on an Altera DE1-SoC through the USB Blaster