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sheepx86 avatar sheepx86 commented on August 23, 2024

The rdtscp instruction (read TSC) is not a serializing instruction. There are possibilities that two rdtscp (with mfence) end up in a negative number. There are a few ways to mitigate this issue, since we are trying to measure "memory latency", some of the methods may affect the result.

What we did was simply disregarding the outliers. See the parsing code at:
src/testscript/parsing/10_parse_basic.py

Reference:
https://www.intel.com/content/dam/www/public/us/en/documents/white-papers/ia-32-ia-64-benchmark-code-execution-paper.pdf

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pocean avatar pocean commented on August 23, 2024

@sheepx86 Thanks for your replying. I disregard the outliers and got the results:
[ 203.766288] {0}Running load-fence-64
[ 206.145701] {0}[0]load-fence-64 avg 1620, stddev^2 37405456, max 9908, min 1000
[ 206.190273] {0}Running ntload-fence-64
[ 208.478466] {0}[1]ntload-fence-64 avg 2702, stddev^2 1695204, max 9988, min 868
My cpu is : Intel(R) Xeon(R) Gold 6246 CPU @ 3.30GHz, so I think the latency of "load-fence-64" is 1000/3.3=303ns. However, according to the paper, the latency of sequential Optane load is ~169ns. In addition, the random Optane read latency I tested have similar results, it seems that there is no buffer on the Optane.

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TheNetAdmin avatar TheNetAdmin commented on August 23, 2024

Hi, have you tried:

  1. Set CPU to 'performance mode', like here:

https://github.com/TheNetAdmin/LENS/blob/663e3f367563e3927edae9a1ee2e840a78977a29/scripts/utils/launch.sh#L33-L36

  1. Turn off cache prefetcher, like here:

https://github.com/TheNetAdmin/LENS/blob/663e3f367563e3927edae9a1ee2e840a78977a29/scripts/utils/launch.sh#L39

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yzouchen avatar yzouchen commented on August 23, 2024

My situation is totally the same, and I already tried Set CPU to 'performance mode and Turn off cache prefetcher.
Cant get a similar result of task 1. Any suggestions?

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