njithjw Goto Github PK

amba_axi_ahb_apb

AMBA bus lecture material

axi-ethernet-uvm

A Verification Platform for UDP Protocol Ethernet Module wrapped with AXI and APB bus based on UVM

axi-vip

VIP for AXI Protocol

axi4vip

AXI4 VIP supports both AXI master and slave.

basic_verilog

Must-have verilog systemverilog modules

bmphandleverilog

BMP file handling Verilog tasks

ebook

电子书

ecc

Verilog for a SECDED Hsaio ECC and a DEC ECC. Power, delay, and area are compared for Berkeley MASIC EEW241B - Advanced Digital Integrated Circuits.

ethernet_10ge_mac_sv_uvm_tb

SystemVerilog-based UVM testbench for an Ethernet 10GE MAC core

fpga

fpga-resource

帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目

gen_amba

AMBA bus generator including AXI, AHB, and APB

genesys_ddr2

DDR2 mem controller for Digilent Genesys Board

h264

H264视频解码verilog实现

ha1588

Hardware Assisted IEEE 1588 IP Core

inputscope

Mouse and keyboard input heatmap visualizer, with statistics.

jpeg-decoder

Verilog Code for a JPEG Decoder

linux-command

Linux命令大全搜索工具，内容包含Linux命令手册、详解、学习、搜集。https://git.io/linux

litepcie

Small footprint and configurable PCIe core

pcie5_phy

PCIE 5.0 Graduation project (Verification Team) under supervision of Mentor Graphics

perlpp

Perl preprocessor - embed Perl source in any file

sd-card-controller

WISHBONE SD Card Controller IP Core

shell_scripts

Shell Scripts examples

stx_cookbook

Altera Advanced Synthesis Cookbook 11.0

uvm_study

study uvm step by step

verilog-axi

Verilog AXI components for FPGA implementation

verilog-axis

Verilog AXI stream components for FPGA implementation

verilog-cam

Verilog Content Addressable Memory Module

verilog-ethernet

Verilog Ethernet components for FPGA implementation

verilog-pcie

Verilog PCI express components