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4way-cache

Verilog cache implementation of 4-way FIFO 16k Cache

accel_int4_mm

altera-cyclone-iv-board-v3.0

Documentation for Chinese ALTERA Cyclone IV EP4CE6 FPGA Development Board

apio

:seedling: Open source ecosystem for open FPGA boards

awesome-canbus

:articulated_lorry: A curated list of awesome CAN bus tools, hardware and resources

awesome-latticefpgas

:book: List of FPGA Lattice boards using open tools

awesome-sky130

A curated list of awesome resources for sky130

basic_verilog

Must-have verilog systemverilog modules

basics-graphics-music-verilator-cocotb-support

FPGA exercise for beginners

bfp

Beyond Floating Point - Posit C/C++ implementation

caravel

Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.

chisel_fma

chiselv

A RISC-V Core (RV32I) written in Chisel HDL

dccontroller

Программное управление блоком питания Agilent E3648A. C#

ddlm

Исходные коды к главам книги "Цифровой синтез: практический курс" (под ред. А.Ю. Романова и Ю.В. Панчула)

digital-design-lab-manual

Digital Design Labs

dsp-theory

Theory of digital signal processing (DSP): signals, filtration (IIR, FIR, CIC, MAF), transforms (FFT, DFT, Hilbert, Z-transform) etc.

eddr3

mirror of https://git.elphel.com/Elphel/eddr3

fpga-webinar-2020

fpga.play.pub

Low cost open source Lattice iCE40UP5k FPGA board.

fpga101-workshop

FPGA 101 - Workshop materials

fpga_101

FPGA 101 lessons/labs

fpu

synthesiseable ieee 754 floating point library in verilog

graph-algorithms

Алгоритмы из книги "Алгоритмы на графах" Роберта Седжвика

green_v

green_v_fpu_posit

hackerrank_python_domain_solutions

Solutions of challenges of Hackerrank Python domain

hackerranksolutions

hdl

HDL libraries and projects

hyperbus

A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs