Could fpgagraphlib support the off-chip DDR memory access ? about fpgagraphlib HOT 4 OPEN

It supports storing edge data in the off-chip memory. However, currently vertex data can only be stored on-chip. You can set the type of memory used in the configuration file:

[arch]
memtype=hmc

Possible values are bram, hmc, or axi. HMC is well-tested (it uses the PicoFramework HMC interface), AXI is not tested much (Xilinx MIG DDR interface was too slow to be worth using).

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Thanks for your response.
I have tried Xilinx MIG DDR interface before, as you said, it is absolutely slow.
So in your opinion, the AXI or Xilinx MIG DDR interface is not recommended ?
Recently, I do not have an FPGA board yet.
I wonder if I want to do some simulation with your work, is it necessary that I must have an FPGA board ?

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The Xilinx MIG I do not recommend. But there are other memory controllers that offer AXI interface with better speed - for example, more recent versions of the PicoFramework have added AXI support to their HMC memory controller, and theoretically I believe the AXI code (in file core_neighbors_axi.py) should work with it. But as I had already built the code to use their custom interface (in file core_neighbors_hmc.py), I continued using this and never tested the AXI with it. The AXI hasn't been used for 2 years so most likely I accidentally made some changes to other code that breaks it.

As for simulation: you can simulate this code using the migen simulator. There are simulation models for the PicoFramework interfaces (HMC, PicoStream, PicoBus) provided in the repository util, so you just need to clone this repo and add the location to your PYTHONPATH. Then, you can do the following:

cd run
python ../src/core_top_pico.py sim

and it will use the settings defined in run/config.ini for simulation (python has to be at least version 3.6). However, the migen simulator is very slow, so you can only simulate very small graphs. Unfortunately the verilog code exported by migen is also not compatible with behavioral simulation, so you cannot use other simulators. You can speed it up a little by using pypy instead of python.

There is another possibility I have not tried: the next generation nmigen has a compatibility layer for old migen code. nmigen can export verilog code that does work well with simulators, so you could e.g. use the PicoFramework simulation facilities (but that requires a ModelSim license), or you would have to provide your own simulation models for the peripherals. If you use only memtype=bram, then it is very simple to build a testbench (e.g. for top_minimal.py, only two input signals are required, the clock and start).
There is also a faster simulator for nmigen being developed currently, but I don't know how complete it is and if the generators from old migen are compatible (for the HMC simulation model).

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Thanks very much for your comprehensive explanations and advices.
I will have a try.

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