STREAM: TX IQ random swap issue about limesuite HOT 6 CLOSED

The issue is related to LMS_StreamBoard::ConfigurePLL(). Disabling it after FPGA PLL is configured correctly, does not make random IQ swapping anymore.
I don't know the exact reason why that's happening, perhaps PLL reset is needed after all those rapid ConfigurePLL calls.

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Definitively still seeing this. Whatever the state machine is, it needs a reset or some kind of enable line to disable during calibration and/or PLL changes.

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The issue arises when FPGA PLLs are configured while LMS7002M CGEN is not configured yet. Then FPGA doesn't get reference clock from MCLK lines and FPGA PLL configuration is messed-up.

Resolution: LMS7002M CGEN must be configured and reference clocks (i.e. MCLK1/MCLK2) must be provided before FPGA PLL configuration.

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I think that then the PLLs are configured, that CGEN has always been configured, and both mclks have something on them. I guess that I am concerned about metastability.

What happens when the CGEN clock rate is changed after the PLL configure? In this case, the mclks will go down temporarily, and change rates. Then the configure PLL call is needed again. How should we handle that case properly?

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New gateware will have FPGA PLL reset, that should solve the problem

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No present issues. Closing.

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