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chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

chisel-bootcamp

Generator Bootcamp Material: Learn Chisel the Right Way

chisel3

Chisel 3: A Modern Hardware Design Language

cnrv-fpu

Basic floating-point components for RISC-V processors

diplomatictester

firrtl

Flexible Intermediate Representation for RTL

fpga-rocket-chip

Wrapper for Rocket-Chip on FPGAs

fpukami

kami

Kami - a DSL for designing Hardware in Coq, and the associated semantics and theorems for proving its correctness. Kami is inspired by Bluespec. It is actually a complete rewrite of an older version from MIT

litmus-tests-riscv

RISC-V architecture concurrency model litmus tests

ltp

Linux Test Project http://linux-test-project.github.io/

maces

Mask Aimed Chisel Expediting System

mill

Your shiny new Java/Scala build tool!

omnixtend

OmniXtend cache coherence protocol

prockami

Kami based processor implementations and specifications

riscv-boom

BOOM: Berkeley Out-of-Order Machine

riscv-coq

RISC-V Specification in Coq

riscv-isa-sim

Spike, a RISC-V ISA Simulator

riscv-linux

RISC-V Linux Port

riscv-opcodes

RISC-V Opcodes

riscv-test-env

riscv-tests

riscv-v-spec

Working draft of the proposed RISC-V V vector extension

riscvspecformal

The RiscvSpecKami package provides SiFive's RISC-V processor model. Built using Coq, this processor model can be used for simulation, model checking, and semantics analysis. The RISC-V processor model can be output as Verilog and simulated/synthesized using standard Verilog tools.

rocket-chip

Rocket Chip Generator

rocket-playground

chipyard in mill :P

spec-impl

stdlibkami

Standard Library of Kami Modules