Implement hardware-accelerated cycle-exact IEC bus controller device about mega65-core HOT 2 OPEN

Standard and JiffyDOS serial protocols are now believed to be working correctly.

There is one work-around, due to a mystery in iec_serial.vhdl where micro_wait() results in double the correct duration of delay when synthesised, compared with under simulation.

See the following blog posts for development log info for this issue:

https://c65gs.blogspot.com/2024/01/hardware-accelerated-iec-serial-bus.html

https://c65gs.blogspot.com/2023/12/hardware-accelerated-iec-serial.html

https://c65gs.blogspot.com/2023/10/hardware-accelerated-iec-serial.html

from mega65-core.

1581/1571 fast serial is being worked on, but is going slowly due to lack of a good disassembly of the 1581 or 1571 ROM, that would make debugging things much easier.

from mega65-core.