- š Iām interested in RTL Design and Design Verification.
- š± Iām currently learning Advanced Bus Protocols, Verification Methodologies and RISC-V Architecture.
- šļø Iām looking to collaborate on ASIC Design, and FPGA projects.
- š« How to reach me : [email protected]
meeeeet Goto Github PK
Name: Meet Sangani
Type: User
Twitter: meeet_sangani
Location: Gujarat,India