Error while compiling about mcudev_devebox_h7xx_m HOT 5 OPEN

The following changes to mpconfigboard.h appear to work:

// HSE is 25MHz
#define MICROPY_HW_CLK_PLLM (25) // divide external clock by this to get 1MHz
#define MICROPY_HW_CLK_PLLN (400) // PLL clock in MHz
#define MICROPY_HW_CLK_PLLP (1) // divide PLL clock by this to get core clock
#define MICROPY_HW_CLK_PLLQ (2) // ...
#define MICROPY_HW_CLK_PLLR (1) // ...

#define MICROPY_HW_CLK_PLL3M (25) // divide external clock by this to get 1MHz
#define MICROPY_HW_CLK_PLL3N (240) // PLL clock in MHz
#define MICROPY_HW_CLK_PLL3P (2) // divide PLL clock by this to get core clock
#define MICROPY_HW_CLK_PLL3Q (5) // divide core clock by this to get 48MHz
#define MICROPY_HW_CLK_PLL3R (2) // ...

After upload, I get:

MicroPython v1.12-659-g441460d81 on 2020-07-26; MCUDEV DEVEBOX STM32H7XX_M with STM32H7XX
Type "help()" for more information.
>>> import machine
>>> machine.freq()
(400000000, 200000000, 100000000, 100000000)
>>>

I'm not 100% convinced this is correct, as it appears that this is running the VCO in wide-range mode, which goes from 2..16 MHz, whereas the divider defined above feeds it with 1 MHz (other values would need changes in µPy code). So maybe it's running out of spec, but this does make the CPU run at 400 MHz, and USB also works.

from mcudev_devebox_h7xx_m.

I slightly change your Clock definitions, to this, according with https://github.com/micropython/micropython/blob/master/ports/stm32/boards/NUCLEO_H743ZI/mpconfigboard.h

#define MICROPY_HW_CLK_PLLM (5) // divide external clock by this to get 5MHz
#define MICROPY_HW_CLK_PLLN (192) // PLL clock in MHz
#define MICROPY_HW_CLK_PLLP (2) // divide PLL clock by this to get core clock 480Mhz
#define MICROPY_HW_CLK_PLLQ (2) // ...
#define MICROPY_HW_CLK_PLLR (2) // ...

#define MICROPY_HW_CLK_PLL3M (5) // divide external clock by this to get 5MHz
#define MICROPY_HW_CLK_PLL3N (48) // PLL clock in MHz
#define MICROPY_HW_CLK_PLL3P (2) // divide PLL clock by this to get core clock
#define MICROPY_HW_CLK_PLL3Q (5) // divide core clock by this to get 48MHz
#define MICROPY_HW_CLK_PLL3R (2)

from mcudev_devebox_h7xx_m.

Save issue.
Please apply the proper patch from proposals above.

from mcudev_devebox_h7xx_m.

#define MICROPY_HW_CLK_PLLP (2) // divide PLL clock by this to get core clock 480Mhz

480MHz is supported if the chip revision is V. In case of revision "Y" maximum clock is 400MHz (errata: https://www.st.com/resource/en/errata_sheet/dm00399555-stm32h750xb-and-stm32h753xi-device-limitations-stmicroelectronics.pdf, 2.2.20 at page 16).

from mcudev_devebox_h7xx_m.

480MHz is supported if the chip revision is V

Yup. And if you just want the highest achievable clock, this can be automated - see my example here:

https://git.jeelabs.org/jcw/jeeh/src/branch/master/arch/stm32.cpp#L110-L116

from mcudev_devebox_h7xx_m.