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Micro Architecture at Santa Cruz (MASC)'s Projects

anubis icon anubis

The ANUBIS benchmark suite for Incremental Synthesis

ariane icon ariane

Ariane is a 6-stage RISC-V CPU capable of booting Linux

bazel_rules_hdl icon bazel_rules_hdl

Hardware Description Language (Verilog, VHDL, Chisel, nMigen, etc) with open tools (Yosys, Verilator, OpenROAD, etc) rules for Bazel (https://bazel.build)

chipyard icon chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

docker-images icon docker-images

UCSC MASC dockerfiles to automate building ESESC, RISCV, LiveHD images

docs icon docs

Documentation for LiveHD and Pyrope

dromajo icon dromajo

RISC-V RV64GC emulator designed for RTL co-simulation

esesc icon esesc

ESESC: A Fast Multicore Simulator

hdlagent icon hdlagent

LLM Agent for Hardware Description Language

hhds icon hhds

Hardware Hierarchical Dynamic Structures

hif icon hif

Hardware Interchange Format

hlop icon hlop

Hardware Logic Operation Library

iassert icon iassert

A better invariant assertion library with gdb support

libelf icon libelf

Fork from https://web.archive.org/web/20181111033959/www.mr511.de/software/libelf-0.8.13.tar.gz (needed by dromajo)

livehd icon livehd

Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation

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