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adc-src-files

avsdadc_3v3

This repository will maintain simulation files, layout files and other relevant files on the SAR ADC worked on in the VSD Summer Online Internship 2020 by the ADC Team.

avsdadc_sky130

10-bit ADC 3.3v analog voltage, 1.8v digital voltage and 1 off-chip external voltage reference.

chatbot-colab

In this repo, I'll put projects that I've done in collaboration with chatbots like OpenAI ChatGPT, Google Bard, etc.

elf-loader

ELF64 Relocatable Object Loader

geneticoptimizer

A DNN built from scratch, featuring multiple fully-connected layers and utilizing the Genetic Algorithm as the optimizer.

gplgpu

Open Source GPU

ldf

Layout Description Framework, a framework to help semi-custom or full-custom designers create the layout of their ICs by writing C# code.

map

MAP

myth-workshop

A 5-day workshop to implement a RISC-V based processor named MYTH from both SW and HW aspects.

nyuziprocessor

GPGPU processor architecture

pasc

Parallel Array of Simple Cores. Multicore processor.

pipelined_6502

A new model to pipeline 6502 processor.

q-tictactoe

Q-Learning based TicTacToe.

risc-v-core

This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve Hoover

rvmyth_avsddac_interface

vsdbabysoc

VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.

vsdbabysoc_mpw3

vsdmemsoc_mpw3

https://caravel-user-project.readthedocs.io

vsdstdcelldesign

This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedures on how to create a custom LEF file and plugging it into an openlane flow.