maheshbhatk Goto Github PK

16ec7g4

VLSI Testing for ICs

apb_bridge

asap

Implementation of ASAP algorithm to a CSV file

atpg_tool_with-ui

Creating a end to end Open source Tool. Runs ATPG Algorithm(PODEM), Testablilty measures(SCOAP Analysis) for the Circuit created by user in Graphical User Interface

covid-vaccine-booking

This very basic script can be used to automate COVID-19 vaccination slot booking on India's Co-WIN Platform. SET FOR BENGALURU

dns-using-cisco-packet-tracer

DNS implementation using Cisco Packet Tracer Software in various configurations.

dvsd-12-bit_adder_using_4-bit_cla

Designing a 12 Bit adder using 4 Bit CLA

i2c

The several codes i have seen so far uses sequential execution of the scl and sda and therefore sda changes when scl is at the edge.But in my code the sda changes only when scl is exactly at zero(Like the actual waveform of the I2C protocol)

i2c_master_slave

Both read and write operation

maheshbhatk.github.io

mytools

Trying to learn new tools

realtimeclock

Real Time Clock(RTC) on 7-segment display.Implementation on FPGA

rtl_practice

Very simple basics using Verilog

rtl_to_gdsii_adder

RTL to GDSII of a 64bit Adder

single_cycle_processor

A single cycle CPU has been constructed in Verilog.

spi

SPI Master and SPI Slave

uart

UART in Verilog.