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sbourdeauducq avatar sbourdeauducq commented on September 20, 2024

As I recall, that broke with a large L, similarly to issue #49. Is that still happening?

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whitequark avatar whitequark commented on September 20, 2024

I've updated the code to use modern ARTIQ:

from artiq import *

class LED(EnvExperiment):
    def build(self):
        self.setattr_device("core")
        self.setattr_device("ttl0")
        self.setattr_device("pmt1")

    def process(self, buf):
        print(buf)

    @kernel
    def run(self):
        L = 20000
        buf = [int(0, width=64) for _ in range(L)]
        self.pmt1.gate_rising(1000*ms)
        count = 0
        for i in range(20000):
            t = self.pmt1.timestamp_mu()
            if t > 0:
                count += 1
            buf[i] = t
        print(count)
        self.process(buf)

It successfully outputs a long sequence of [-1]s with L<=20000, and raises an RTIOUnderflow with Ls>=30000. Is that the expected behavior?

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sbourdeauducq avatar sbourdeauducq commented on September 20, 2024

No, -1 means no rising edges were detected - did you connect the 1MHz generator?

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whitequark avatar whitequark commented on September 20, 2024

No, I have no idea what to connect, and also I'm not in the lab...

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whitequark avatar whitequark commented on September 20, 2024

I tried to add a TTLClockGen on 19th channel, still no effect:

from artiq import *

class LED(EnvExperiment):
    def build(self):
        self.setattr_device("core")
        self.setattr_device("ttl0")
        self.setattr_device("ttl_sma")
        self.setattr_device("ttl_clock")

    def process(self, buf):
        print(buf)

    @kernel
    def run(self):
        L = 20000
        buf = [int(0, width=64) for _ in range(L)]
        self.ttl_sma.gate_rising(1000*ms)
        self.ttl_clock.set_mu(1000)
        count = 0
        for i in range(20000):
            t = self.ttl_sma.timestamp_mu()
            if t > 0:
                count += 1
            buf[i] = t
        print(count)
        self.process(buf)

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sbourdeauducq avatar sbourdeauducq commented on September 20, 2024

The 10MHz clock on SMA I'm talking about is built into the gateware and driven here:
https://github.com/m-labs/artiq/blob/master/artiq/gateware/targets/kc705.py#L37

The SMA TTL is here:
https://github.com/m-labs/artiq/blob/master/artiq/gateware/targets/kc705.py#L168

The clock generator on channel 19 is a different pin (it's on the FMC and relatively hard to connect), and it won't feed into the SMA TTL unless you connect it physically.

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whitequark avatar whitequark commented on September 20, 2024

@sbourdeauducq, so would you test this?

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sbourdeauducq avatar sbourdeauducq commented on September 20, 2024

Affected by a similar problem as #228 now...

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whitequark avatar whitequark commented on September 20, 2024

#228 was fixed, does this work now?

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sbourdeauducq avatar sbourdeauducq commented on September 20, 2024

I'm pretty sure this works, but I'd be paranoid and test it anyway.

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sbourdeauducq avatar sbourdeauducq commented on September 20, 2024

Works but timestamps are affected by #286.

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