Wrong behavior of asynchronous RAM reads in generated VHDL about logisim-evolution HOT 4 OPEN

@@ -44,8 +44,10 @@ public class RamHdlGeneratorFactory extends AbstractHdlGeneratorFactory {
     final var async = StdAttr.TRIG_HIGH.equals(trigger) || StdAttr.TRIG_LOW.equals(trigger);
     final var ramEntries = (1 << nrOfaddressLines);
     final var truncated = (nrOfBits % 8) != 0;
+    if (byteEnables) {
+      myWires.addWire("s_ramdataOut", nrOfBits);
+    }
     myWires
-        .addWire("s_ramdataOut", nrOfBits)
         .addRegister("s_tickDelayLine", 3)
         .addRegister("s_dataInReg", nrOfBits)
         .addRegister("s_addressReg", nrOfaddressLines)
@@ -120,9 +119,11 @@ public class RamHdlGeneratorFactory extends AbstractHdlGeneratorFactory {
               inputRegs : {{process}}({{clock}}, {{tick}}, address, dataIn, we, oe) {{is}}
               {{begin}}
                  {{if}} (rising_edge({{clock}})) {{then}}
+                    {{if}} ({{tick}} = '0') {{then}}
+                        s_addressReg <= address;
+                    {{end}} {{if}};
                     {{if}} ({{tick}} = '1') {{then}}
                         s_dataInReg  <= dataIn;
-                        s_addressReg <= address;
                         s_weReg      <= we;
                         s_oeReg      <= oe;
               """);
@@ -182,7 +183,7 @@ public class RamHdlGeneratorFactory extends AbstractHdlGeneratorFactory {
                       {{if}} (s_we = '1') {{then}}
                          s_memContents(to_integer(unsigned(s_addressReg))) <= s_dataInReg;
                       {{end}} {{if}};
-                      s_ramdataOut <= s_memContents(to_integer(unsigned(s_addressReg)));
+                      dataOut <= s_memContents(to_integer(unsigned(s_addressReg)));
                    {{end}} {{if}};
                 {{end}} {{process}} mem;
                 """);
@@ -206,18 +207,6 @@ public class RamHdlGeneratorFactory extends AbstractHdlGeneratorFactory {
               .add("   {{end}} {{if}};")
               .add("{{end}} {{process}} res{{1}};", i);
         }
-      } else {
-        contents
-            .add("""
-                res : {{process}}({{clock}}, s_oe, s_ramdataOut) {{is}}
-                {{begin}}
-                   {{if}} (rising_edge({{clock}})) {{then}}
-                      {{if}} (s_oe = '1') {{then}}
-                        dataOut <= s_ramdataOut;
-                      {{end}} {{if}};
-                   {{end}} {{if}};
-                {{end}} {{process}} res;
-                """);
       }
     }
     return contents.empty();