Related Issues (20)
- [FIRRTL] InferResets: does not catch uninferred abstract resets
- [FIRRTL] FART: not totally idempotent - but may be close enough HOT 1
- [FIRRTL] FullAsynchronousResetTransform should be moved out of InferResets
- [FIRRTL] FART: when annotated reset is under a when, always leads to uninitialized wires
- [FIRRTL] InferResets: extmodules should not be allowed to have abstract resets HOT 1
- [FIRRTL] FART: Should not modify public module ports
- [SV] Add option to generate ram blocks without x assigns HOT 1
- [ESI] Add value validation to Channels and Bundles
- [FIRRTL] Inconsistency when compiling two semantically equivalent fir code HOT 2
- Main link on GH broken (circt.org rather than https://circt.llvm.org/) HOT 1
- Perf measurements link (https://circt.org/perf/) broken HOT 1
- [FIRRTL] Replace "noRefTypePorts" with Pass
- [README] what does "IR" stand for? HOT 1
- [FIRRTL] Feature Request: Have dedup report all errors, not just the first HOT 1
- [FIRRTL] Crash in LowerClasses related to StringMap buckets HOT 1
- [FIRRTL] Investigate LowerClasses namespace lifetimes
- [firtool] Not parsing enable/disable layers CLI option properly
- [LowerToHW] Crash involving `TestBenchDirAnnotation` HOT 1
- [FIRRTL] Incorrect Output Directory for Multiply Instantiate Module in Layer
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