Comments (5)
Yeah I'd love to see this. I'm not sure the best way to handle this. The existing lowering pass is parallel across FModuleOp
s, so it isn't supposed to touch the enclosing CircuitOp
. I think it would make sense to keep this, but then add a subsequent pass over the CircuitOp
that lowers the modules. This allows parallelism across the module level, and then a quick cleanup pass that lowers the modules themselves.
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@River707 does this seem sensible to you? Any precedent we should be aware of here?
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I was wondering the same thing for the FIRRTL-to-LLHD pass. It currently runs on CircuitOp
, but running in parallel on FModuleOp
and doing a cleanup pass as @lattner suggests is a great idea.
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I'm going to take a look at this
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Finally landed in fcf8f8b !
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Related Issues (20)
- [FIRRTL] Dialect/FIRRTL/lower-dpi-error.mlir failed in nightly integration tests HOT 1
- [CI] ccache doens't work on nightly integration tests HOT 6
- [CMake] Installation fails if SLANG_ENABLE_FRONTEND is enabled HOT 13
- [SimToSV] Lowering fails if a DPI call result is consumed by another
- [SV][HW] Introduce hw::HWFunctionType and use it for Sim/SV function ops
- [FIRRTL] Unsafe parallel mutation of IR in SpecializeLayers HOT 5
- [CMake] Both local install and compiled release usages failing HOT 2
- [Seq] Unify HLMem and FIRMem HOT 2
- [ImportVerilog] Upgrade slang to slang 5
- [Seq] FirReg is not appropriate for the seq dialect
- [Seq] Add reset type
- CombDataflow op interface should not exist in the HW dialect HOT 1
- [FIRRTL] LowerLayers creates empty port names, preventing round-trip
- [FIRRTL] InferResets: deleting op used to drive reset network results in use-after-free
- [FIRRTL] Add optional arg name to DPI-C functions
- [FIRRTL] DPI type check should not check the reference type. HOT 2
- [FIRRTL] Constant will be elimated on the DPI Path HOT 3
- [FIRRTL] When passing Reg to DPI, it will trigger the comb logic cycle error.
- [Arcilator] Performance Issue HOT 2
- [CI] Nightly integration test failure HOT 13
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