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accdnn

A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.

bnn-fpga

Binarized Convolutional Neural Networks on Software-Programmable FPGAs

chaidnn

HLS based Deep Neural Network Accelerator Library for Xilinx Ultrascale+ MPSoCs

deep-neural-network-hardware-accelerator

SystemVerilog HDL and TB code Deep Neural Network Hardware Accelerator implementation on zybo 7010 FPGA and also C code for Vivado SDK Software

digital-design-lab

diracdeltanet

PyTorch implementation of DiracDeltaNet from paper Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs

dota_yolov2

fpga-dcnn-accelerator

基于HLS的高效深度卷积神经网络FPGA实现方法

hls_for_cnn

This repo has codes for hardware accelerator design for CNNs using high level synthesis from Altera.

hw

RTL, Cmodel, and testbench for NVDLA

incubator-tvm

Open deep learning compiler stack for cpu, gpu and specialized accelerators

lenet_accelerator

A Lenet ASIC Accelerator targeting minimum number of cycles

pwc

Papers with code. Sorted by stars. Updated weekly.

shufflenet-v2-pytorch

Perfect implement. Model shared. x0.5 (Top1:60.646) and 1.0x (Top1:69.402).

shufflenet_v2_pytorch_caffe

ShuffleNet-V2 for both PyTorch and Caffe.

shufflenetv2-ncnn

ShuffleNet_V2 for ncnn framework

shufflenetv2-pytorch

Implementation of ShuffleNetV2 for pytorch

shufflenetv2_hls

A FPGA-based Accelerator for Shufflenetv2 implemented on Xillinx Zynq-7000 SoC

spatial-multiverse

Provides Spatial with front-end support from popular machine learning frameworks

squeezenet

squeezenet-1

SqueezeNet: AlexNet-level accuracy with 50x fewer parameters

squeezenext

yolov2_xilinx_fpga

A demo for accelerating YOLOv2 in xilinx's fpga pynq/zedboard

zju-icicles

浙江大学课程攻略共享计划