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arch_sec_papers

bighuang624.github.io

学术主页 | Academic Page

cache-side-channel-attack-on-gnupg

In this task, I have performed the FLUSH+RELOAD attack on GnuPG cryptography Library to observe accesses to critical functions like Square (S), Module (r), and Multiply (M) function during the encryption or decryption process of the RSA algorithm. In this project, Gogo will mount a side-channel attack with a goal to leak the critical accesses of Gollu.

cache_template_attacks

This repository contains several tools to perform Cache Template Attacks

chisel-bootcamp

Generator Bootcamp Material: Learn Chisel the Right Way

cleanupspec

CleanupSpec (MICRO-2019)

flush-reload-attacks

frameworks

gem5

This is an read-only mirror of the gem5 simulator. The upstream repository is stored in https://gem5.googlesource.com, code reviews should be submitted to https://gem5-review.googlesource.com/. The mirrors are synchronized every 15 minutes.

gem5-pf

invisispec-1.0

Gem5 implementation of "InvisiSpec", a defense mechanism of speculative execution attacks on cache hierarchy.

latex-template-collection

Collection of different LaTeX/XeTeX templates (cv, invoices, timesheets, letters, etc.).

learn-gdb-by-example-for-c

learn gdb by example | gdb 教程 例子

learn-llvm-12

《Learn LLVM 12》的非专业个人翻译

learn_prefetcher

hardware & software prefetcher

limengming.github.io

Github Pages template for academic personal websites, forked from mmistakes/minimal-mistakes

llvm-project

The LLVM Project is a collection of modular and reusable compiler and toolchain technologies. Note: the repository does not accept github pull requests at this moment. Please submit your patches at http://reviews.llvm.org.

masterrtl

MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design

meltdown

This repository contains several applications, demonstrating the Meltdown bug.

myhuancun

pl-compiler-resource

程序语言与编译技术相关资料（持续更新中）

primeprobe

rcore-tutorial-v3

Let's write an OS which can run on RISC-V in Rust from scratch!

rtllm

An open-source benchmark for generating design RTL with natural language

xiangshan

Open-source high-performance RISC-V processor