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chatgpt

Reverse engineered ChatGPT API

cordic_cpp

A series of CORDIC related projects

corundum

Open source, high performance, FPGA-based NIC

dblclockfft

A configurable C++ generator of pipelined Verilog FFT cores

directnvm

An open-source RTL NVMe controller IP for Xilinx FPGA.

elec5882

The Design and Implementation of a Pulse Compression Filter on an FPGA.

embeddedsw

Xilinx Embedded Software (embeddedsw) Development

nvme_comp_storage

Computational Storage Device based on the open source project OpenSSD.

nvmecha

NVMe Controller featuring Hardware Acceleration

nvmedirect

riffa

The RIFFA development repository

ssd_test

SSD test project using Zynq Ultrascale+ bare metal NVMe.

tlast_generator

Implementation of a TLAST signal in an AXI Stream.

unvme-zynq

User Space NVMe Driver (modified for use on Zynq UltraScale+ MPSoC)

verilog-axi

Verilog AXI components for FPGA implementation

verilog-axis

Verilog AXI stream components for FPGA implementation

verilog-dsp

Verilog digital signal processing components

verilog-ethernet

Verilog Ethernet components for FPGA implementation

verilog-i2c

Verilog I2C interface for FPGA implementation

verilog-pcie

Verilog PCI express components

verilog-uart

Verilog UART

vivado-project-template

Template for Xilinx Vivado projects

wave-vivado

HDL and C source for WAVE Zynq Ultrascale+ SoC

wb2axip

Bus bridges and other odds and ends

zedboard_axi4_master_burst_example

Quick Example how to generate an custom AXI4 IP with AXI4-Full interface (burst) for the Zynq (ZedBoard)