khoalydang Goto Github PK
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khoalydang's Projects
5g-nr-ldpc
5G NR LDPC MATLAB implementation
5g-nr-polar
A 3GPP 5G NR compliant Polar code library, which is a slight modification of https://github.com/robmaunder/polar-3gpp-matlab.
basic-simd-processor-verilog-tutorial
Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clock cycle will be used to load values into the registers. The second will be for performing the operations. 6-bit opcodes are used to select the functions. The instruction code, including the opcode, will be 18-bit.
face3d-pytorch
3D Face Recognition, implemented with PyTorch
ieee-754-floating-point-multiplication-using-weighted-2-stage-booth-algorithm
This is a project to design and implement a IEEE 754 Floating-point standard multiplication using Weighted 2_stage Booth algorithm to improve its performance in comparison with traditional method (array multiplication). More information of this project can be found on PowerPoint file.
ip-cores
A huge collection of VHDL/Verilog open-source IP cores scraped from the web
ofdm
OFDM modem
phase-locked-loop
We are designing a CP-PLL. The following link provides resources about PLL design.
turbo-3gpp-matlab
Matlab simulations of the encoder and decoder for the LTE turbo code from 3GPP Release 15
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