riffa python example showed different data between TX and RX buffers about riffa HOT 3 OPEN

@jixi2018 This is normal. The demo bitstream is built with minimal RTL code, just for timing evaluation and testing purposes. The contents of a data buffer is reused internally when switching from Rx to Tx, so the last 4 values received are sent back (for128b PCIe bitstreams).
The demo RTL is a good point to start hacking and add your own functionality, though.

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hi, sorry to bother you, but in my riffa system, the linux just cannot find a riifa device,
so , can you please tell me : do I need install PCIe driver for the riifa when i had installed the riifa driver ??

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@marzoul, Thanks for the reply. I am going to locally modify the chnl_tester.v to add a BRAM block and other logics to buffer the RX data, perform some processing. Then it will send the data in BRAM back via TX. There are RX/TX signals at the chnl_tester.v top-level. Could you let me know the timing of the following ones:

input CHNL_RX,               //is this a pulse to start RX or should it be active during the whole RX?
input CHNL_RX_LAST,     //same, is this a pulse asserted at the last RX word(128-bit)

output CHNL_TX_LAST,          //the example set it to constant 1, it is true for all cases?

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