Comments (1)
I think this has been done. I see the following:
Register 6 failed to match. Was 0. Should be 1234
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Related Issues (20)
- Add documentation for stage registers
- Bug in subword memory access in combinational memory port HOT 2
- Tests to add
- Chisel Notes: First Hardware discrepancy HOT 5
- Merge improvements from sq20
- Migrate from travis to github actions HOT 1
- Move default branch to main from master
- Fix diagram for assignment 3
- Update Chisel to 3.4 HOT 3
- Understanding the use of TreadleTester in CPU simulation HOT 9
- Question about Local Branch Predictor HOT 1
- Update docker container for gradescope
- Fix first-hardware.md missing import HOT 1
- Upstream fix for #120 HOT 1
- Fix test commands in Lab tests
- Fix PC width issue HOT 1
- Support rv64i HOT 1
- Add a diagram for single-cycle dinocpu
- Fix non-combinational pipelined cpu
- Fix the behavior of non-combin memory
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