Comments (7)
I think i am the first one to comment on this!
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It'll compute a hash every 64 cycles per core, so it depends on your clock speed.
This was designed on/for the iCE40HX8K-BG121 which currently can only support 2 cores at 30MHz. So roughly 0.9~1 MH/s.
However, the logic is deep. It performs a hash round every cycle. You can likely go faster with more pipelining at the expense of space on the FPGA. Not sure yet which choice would come out on top.
Some other optimizations, like putting the message in block RAM (#4), could save some room and potentially bring the number of cores to 4 -- so 1.9~2 MH/s.
The icepool project allows to cluster multiple iCE40HX8K's. One motherboard with 16 FPGAs would be about 14~15 MH/s.
In conclusion, not very fast.
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Per core how many LUTs? for ICE40?
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And if we have 50mhz clock then it would be more speed right?
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The iCE40s have 7680 "logic cells." The cores share these with the I/O logic (2xSPI, control signals, state machine, etc.) so hard to say exactly. I think I can fit 3 cores and I/O into 7680 (if I recall correctly) but the logic divides the work up into powers of 2, so 3 doesn't work well.
And yeah, more cycles / second means more hashes / second.
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you know about the esp32?
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https://www.efinixinc.com/products-titanium.html
Ti35
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Related Issues (20)
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- Tests using `libftdi` HOT 1
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