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brent-kung-adder

Python code for genrating Brent Kung Adder in verilog(.v)

canny-advanced

canny advanced verilog 1280*720 15fps

canny-using-verilog-for-size-200

canny verilog 200*200 260ms

cook

🍲 好的，今天我们来做菜！OK, Let's Cook!

cordic

An implementation of the CORDIC algorithm in Verilog.

cordic-1

The CORDIC algorithm implemented in Octave/MATLAB and Verilog

cordic-2

Cordic 算法实现

coursera-ml-andrewng-notes

吴恩达老师的机器学习课程个人笔记

deep-learning-book-chapter-summaries

Attempting to make the Deep Learning Book easier to understand.

deeplearning.ai-summary

This repository contains my personal notes and summaries on DeepLearning.ai specialization courses. I've enjoyed every little bit of the course hope you enjoy my notes too.

digital_adders_verilog

32 Bit RippleCarry, CarrySkip, CarrySelect, CarryIncrement, Sklansky, Brent-Kung, Kogge-Stone and CarryLookahead adders with their internal components in Verilog

fpu

synthesiseable ieee 754 floating point library in verilog

fpu-1

open FPU project. 32/64 bit FPU in Verilog

fpu-2

han-carlson-adder

code for printing verilog code of han carlson adder for n bits in python as well as java both.

hearthstone-deck-tracker

A deck tracker and deck manager for Hearthstone on Windows

hitsz-daily-report

基于Github Action的定时HITsz疫情上报脚本，开箱即用

iverilog

Icarus Verilog

koggestone-brentkung

gate level implementation of Kogge-Stone and Brent-Kung adders

ksa

Kogge-Stone Adder in Verilog

pynq_softmax

achieve softmax in PYNQ with heterogeneous computing.

real-time-sobel-edge-detector-in-fpga

Academic project within the discipline of Digital Systems using a Terasic Altera DE2 Development Board

sobel

Implementation of Sobel Filter in Verilog

sobel-filter

Hardware accelerator design in Verilog for a Sobel operator. Implemented and tested on a Xilinx FPGA.

verilog_cordic_core

configurable cordic core in verilog