jayram711 Goto Github PK

followers: 24.0 following: 35.0 repos: 6.0 gists: 0.0

Name: J Λ Y

Type: User

Company: Sathybama Institute of Science and Technology

Bio: VLSI Enthusiast | Student at SIST | Ex-Executive @Robotics-Club-SIST | Trainee at MAVEN SILICON

Location: chennai

Blog: https://linktr.ee/Jayaram711

J Λ Y's Projects

100-days-of-rtl

This Repo contains Codes of RTLs for implementation of various circuit designs using Verilog in Xilinx ISE 14.7 and sometimes Modelsim tools

ahb2apb-protocol-bridge

The AHB to APB Bridge is an AHB slave, providing an interface between the high-speed AHB and the low-power APB. Read and Write transfers on the AHB are converted into equivalent Transfers on the APB

fpga-projects

This repository contains the files related to Implementations of various Digital circuits on the NEXYS A7 FPGA Board

fsm-mini-projects

This Repo contains Source Codes of FSM-BASED implementation of various circuit designs using Verilog in Xilinx ISE 14.7 and sometimes Modelsim tools

hdl-bits

This Repo consists codes for some the problem statements from the HDL BITS website and can help you in your journey to learn Verilog from the scratch

inverter-design-and-analysis-using-sky130pdk

CMOS inverter schematic and layout design and analysis utilizing the skywater 130 nm pdk and numerous open source tools such as Xschem, NGSPICE, MAGIC, Netgen, and so on.

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