Issues with the SRAM Circuit about amiga-2000-eatx HOT 7 CLOSED

This revised RAM circuit was implemented on Rev 1.1 and seems to work perfectly, according to diagrom.

Thanks everyone for your help!

from amiga-2000-eatx.

Hey @jasonsbeer
I hadn't even thought about DRA9 that's a good point!

2*256Kx16s would work well, a 512Kx16 would work too and would mean that the OR gate (U3 in the original design) is no longer needed, you'd be able to just connect _sramce to the srams chip select I think

The changes I made to the design and why, also relevant the timing diagrams Here

• Added second latch (U7) for upper address bits - As shown on the timing diagram, the address pins change while CAS is still asserted, but we need to keep the address stable while SRAMCE is active
• Removed RAS from SRAMCE so it's just CAS - As shown on the timing diagram, RAS deasserts early which means SRAMCE would deassert before the ram cycle is complete, CAS always comes after RAS so RAS isn't needed as part of the SRAMCE equation anyway
• MA8 was not connected to the ram, A8 was connected instead to both pins 19 and 28 of the SRAMs
• Because CE's are NAND'ed with the BDRA9 which isn't latched, this will also cause _ceu4/5 to deassert when the address bus changes, in my updated design the nand input uses MA19/INVMA19 instead which are latched by U7 so they remain stable throughout the memory cycle

with some patience you can bodge things and make it work with the original design :)

from amiga-2000-eatx.

Hi @LIV2 , I've been consulting @jasonsbeer on this issue. Thanks for providing this data. I took a preliminary updated schematic provided by @jasonsbeer and marked it up based on your input and my reverse engineering of the A2000 chipram circuit. If you have a chance, I wouldn't mind another set of eyes and an opinion if you think this more changes are needed.

Summary of changes:

• @jasonsbeer added a latch for the column address, latched on CAS (derived from /CASx inputs)
• Changed _SRAMCE so it is just an inversion of CAS. SRAM is now selected independent of /RASx signals.
• A8 is tied to pin 19 and 28 of the SDRAM via the latches (depending on if A8 is the row or column address) (by @jasonsbeer)
• This would appear to be unique to using 2 chips, however /RAS1 is now latched (which will serve as A18*) based on the statement that "RAS deasserts early". Effectively this will serve as the 19th address line to select which half of the SRAM will be accessed (functionally equivalent to asserting /RAS0 or /RAS1 which selects the top or the bottom row of DRAM chips).
• NOTE: The OR circuit in your design is eliminated since we don't have an A19 or a second SRAM chip to address.

Question (while we're at it): Do you know why the series resistors and pull ups are present in this circuit? There are no stubs here so they don't seem to be necessary for bus termination. The only reason I can think of would be because the original DRAMS presented too much of a load for 74xxx logic, or were needed to correct an impedance mismatch. I suspect these can be removed as well. I noticed they are not in your schematic, have you seen any ill effects from this?

*Based on the A500 schematics here, it would appear /RAS1 and DRA9 are the same signal - see pin 56 of the Agnus chip, although it appears to me that either /RAS0 or /RAS1 would serve this function.

IMG_20210522_0001.pdf

from amiga-2000-eatx.

Hi @texneus

All of the above looks correct to me and I believe that if implemented as described it should work well.
I'd probably spec something like 74AHCT244's instead of HCT for U540/541 though as it has a prop delay closer to the original's F244s and the timing may be critical.

Question (while we're at it): Do you know why the series resistors and pull ups are present in this circuit? There are no stubs here so they don't seem to be necessary for bus termination. The only reason I can think of would be because the original DRAMS presented too much of a load for 74xxx logic, or were needed to correct an impedance mismatch. I suspect these can be removed as well. I noticed they are not in your schematic, have you seen any ill effects from this?

For the A500+ SRAM board this wasn't a consideration - since it plugs into an A500+ mainboard which would already have the resistors etc.
I'm not 100% sure what they're used for but the 74F244's in the original A500/2000's have quite a fast transition time and strong drive current so any impedance mismatching, ringing etc might be bad enough to damage the old DRAMs they used back then.
I'd probably leave it in the design just in case there are other concerns like stability etc.
I'd say the pull-ups would be to help give a faster rise time of the address signals, especially needed with 74F244's that can drive 64mA for output low but only 12mA high

*Based on the A500 schematics here, it would appear /RAS1 and DRA9 are the same signal - see pin 56 of the Agnus chip, although it appears to me that either /RAS0 or /RAS1 would serve this function.

Yep exactly, either one works for this purpose just fine

from amiga-2000-eatx.

Great discussion! I very much appreciate both your time on this. I have no doubt we have a solid plan and I will make these changes on the next revision. Now...how to bodge this together on the current revision...

I'll leave this issue open until we have a working prototype in hand.

from amiga-2000-eatx.

@LIV2

Thank you for this valuable information. Unfortunately, fabrication of the current revision is nearly complete. I will need to include your proposed changes in a new revision. Any speculation on why the original circuit does not work?

Thank you for your generous offer of the Agnus adapter. Unfortunately, I do not have an 8375. I think is is unlikely I will be able to obtain one. They seem rarely available and expensive when they are.

from amiga-2000-eatx.

Hi @LIV2

I reviewed the schematic you supplied. Obviously, there are differences between the Rev 6.x A2000 and the A500+ in the amount of chip ram that can be addressed. The A500+ (with 8375) supplies signal DRA9 and has 10 memory address lines. The 1 MB Agnus does not supply signal DRA9 and has 9 memory address lines.

I'm thinking the best solution is to use a different SRAM IC. 256k x 16 memory chips have 18 address lines, so they match up well that way and we do not have extra address connections we need to figure out. One example is attached. Happy to hear your thoughts. Thanks!

AS6C4016.pdf

from amiga-2000-eatx.