FSP DRAM configuration for memory with only single channel about fsp HOT 4 OPEN

On Tue, Jul 7, 2020 at 4:43 AM Maurice Ma ***@***.***> wrote: Hi, Mahesh, Maybe you already know that the memory configurations are highly tied to the board design. And the board design needs to follow the APL platform design guide. In your case, you used single rank device on single channel (assuming you are using LPDDR3 or LPDDR4), I am not sure if it is currently supported or not. All Intel's CRB board designs have more than 1 channel. If you look into some old APL EDS volume 1 doc, you will see it listed supported memory configurations for APL. It stated two channels are supported for "populating CH00 and CH01" and "populating CH10 and CH11". And it also clearly stated "Single 32 bit channel" is not supported. The latest EDS has removed that and stating it can support LPDDR4 memory configuration on CH0 (CH0_CQB) only. Have your board team consulted Intel representative on this board design to ensure it follows the platform design guide ? They might be able to share some of the info on how to provide correct memory configurations as well. — You are receiving this because you authored the thread. Reply to this email directly, view it on GitHub <#52 (comment)>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/AOHJYGBCWNFRZW7OU6N33J3R2JLB5ANCNFSM4ORJBJGA> .

On Tue, Mar 30, 2021 at 12:23 AM Siva Prakash ***@***.***> wrote: Any updates to the issue ? whether Intel FSP supports Single Rank configuration? — You are receiving this because you authored the thread. Reply to this email directly, view it on GitHub <#52 (comment)>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/AOHJYGC2FTYSTPGF4T2JLSTTGDLD7ANCNFSM4ORJBJGA> .