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500lines

500 Lines or Less

autovote

Automated scripts for voting on websites, for my cousin sister.

baiyan_profile

My custom run commands (.*rc) file for bash, vim & etc. from server in Baiyan

cp_autoscr

Automated scripts for my project Calibration Path

filesynscript

in order to synchronize the files between several computers

fpu

gesturerecognition_verilog

Identifies ASL Hand Gesture for numbers using image processing in verilog

gitignore

A collection of useful .gitignore templates

jpeg2000_serial

JPEG2000 compression coder on Xilinx Virtex 5 FPGA

latex-template-cn

\LaTeX 中文模版收集。

molokai

Molokai color scheme for Vim

my_vimrc

netlist_parser.py

A Python based netlist parser, including Verilog and SPICE

netlist_parser.py-1

A Python based netlist parser, including Verilog and SPICE

pt-help

pymtl

Python-based hardware modeling framework

pyspice

Simulate electronic circuit using Python and the Ngspice / Xyce simulators

pyverilog

Python-based Hardware Design Processing Toolkit for Verilog HDL

pyverilog-1

Python-based Verilog Parser (currently Netlist only)

recycledic_pltscr

Ploting scripts for my project Recycled IC

simplenetlist

This repository contains a simple model for representing netlist (electronics) in python

some-useful-perl-scripts

These scrpits will be extremly useful in parsing Verilog files

verilog-automatic

Automatically generate verilog module ports,instance and instance connections ,for sublime text 2&3

verilog_labs

verilog_labs in eecourse

vundle.vim

Vundle, the plug-in manager for Vim

yafsm

Yet Another FSM - Perl base code generator (c++) for Finite State Machines