Related Issues (20)
- Overlapping vias in IO cell HOT 3
- DRC violation in sealring HOT 5
- Mention OpenROAD & in support tools HOT 4
- how was the layout versus scheme verification done ... HOT 2
- Does this have MEMRES model? HOT 3
- UDP and SDF forbids post-synthesis simulation with either Icarus Verilog or Verilator HOT 8
- Statistical modeling with parameter mc_ok HOT 1
- qucs-s simulation with xyce HOT 23
- Cloning the submodule `digital` fails HOT 6
- MOS Devices Tests Aren't Working. HOT 7
- MOSFET PSP model usage of NF parameter HOT 4
- Routing issue in `dfrbp_1` flop HOT 2
- Fix pin labels in `a221oi_1` cell
- Any Recomended Python Versions? HOT 5
- 32x32 SRAM
- sram: missing .lib files HOT 5
- Stdcell schematics should contain multiplier = 1
- Missing Analog Pad cell from Liberty views
- Filler cells are missing in CDL/SPICE netlists
- large increase in area for ff compared to buf for upsize HOT 2
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