gagana-05 Goto Github PK

100daysofrtl

I was inspired by @raulbehl challenge to code a module everyday and progressively improve on coding skills. So here I am giving it a shot!

6th-sem

ngl I do give some credits to chatGPT XD

af_website

apb_protocol

irony I tried to learn the logic of APB bus, before googling it's full form its Advanced Peripheral Bus guys! :p

axi_dma

General Purpose AXI Direct Memory Access

azadi-soc

Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.

caravel-sim-infrastructure

caravel_cocotb

caravel_cocotb_verification_tutorial

caravel_setup

cvw

CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.

floating-point-alu-in-verilog

32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.

fpga_basics

fpu

synthesiseable ieee 754 floating point library in verilog

gagana-05

Config files for my GitHub profile.

gagana-05.github.io

i2c

I2C controller core

image_captioning

impulse_workshop

ode_solver

VLSI Mini Project

opencv-course

Learn OpenCV in 4 Hours - Code used in my Python and OpenCV course on freeCodeCamp.

picorv32

PicoRV32 - A Size-Optimized RISC-V CPU

pulpissimo-ptf

This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.

risc-v-cpu-core

This repo contains the codes which I implemented while completing the course "Building a RISC-V CPU Core" offered by Linux Foundation through edx.

risc-v-soc

SoC project

runs_caravel

Adding some simple runs here

serialadder

Parameterized Serial Adder

term-project

vlsi-lab-2022

vlsi_design-of-risc

IEEE Executive project for the year 2021-2022