Gagana's Projects
I was inspired by @raulbehl challenge to code a module everyday and progressively improve on coding skills. So here I am giving it a shot!
ngl I do give some credits to chatGPT XD
irony I tried to learn the logic of APB bus, before googling it's full form its Advanced Peripheral Bus guys! :p
General Purpose AXI Direct Memory Access
Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.
CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.
32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.
synthesiseable ieee 754 floating point library in verilog
Config files for my GitHub profile.
I2C controller core
VLSI Mini Project
Learn OpenCV in 4 Hours - Code used in my Python and OpenCV course on freeCodeCamp.
PicoRV32 - A Size-Optimized RISC-V CPU
This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.
This repo contains the codes which I implemented while completing the course "Building a RISC-V CPU Core" offered by Linux Foundation through edx.
SoC project
Adding some simple runs here
Parameterized Serial Adder
Playground for VGA projects on Tiny Tapeout