featherweight-ip Goto Github PK
Type: Organization
Type: Organization
Website for the Featherweight-IP Project
Docker image containing the tools used for Featherweight-IP functional verification
Implements a simple local-interrupt controller for up to 30 external and 1 software source
Utility design blocks with ready/valid interfaces
Provides SRAM subsystems built from SKY130 SRAM blocks
Various Wishbone bridges
Parameterized Wishbone interconnect
Wishbone SRAM controllers, including support for atomic operations
Generic SRAM primitives with specializations for FPGA targets
Simple GPIO component with support for pin muxing
Scripts to generate an interconnect from a specification
Library of sub-components used by other IPs
Parameterizable network on chip designed to be tiled
Provides a configurable NxM cache-coherent fabric generator.
Banked SRAM controller that uses the Fwnoc protocol
Bridges between fwnoc and wishbone protocols
Provides a simple peripheral-capable DMA engine
Featherweight programmable interrupt controller (PIC)
Programmable Interval Timer
SystemVerilog macros for standard protocols
Featherweight RISC-V implementation
Cluster of fwrisc cores
Featherweight SDRAM controller
Simple differential-signaling SERDES block with clock recovery
SPI initiator IP
Read-only memory interface to spi flash devices
Interfaces stubs that leave interfaces active for IP synthesis
Featherweight UART IP
UART 16550 packaged for featherweight IP
Provides several configurations of VexRISC as FeatherweightIP packages
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