ekanshbhatnagar Goto Github PK

basic_verilog

Must-have verilog systemverilog modules

c-plus-plus

All Algorithms implemented in C++

chatroom

Simple Socket Chatroom in Python

classesmd5-64

Extract classes.dex from apk and returns base64 MD5 raw encoded

contribute-to-open-source

Learn the GitHub workflow by contributing code in a fun simulation project

damweb

diy_li-fi

dockerfiles

Dockerfiles for Travis builds and cross-compilation.

dotfiles

My linux dotfiles

driver-drowsiness-and-yawn-detection

dwm

Luke's build of dwm

filtercsv

Tools to manipulate CSV files in a format suitable for importing into various mindmapping programs - such as iThoughts, Freemind, and MindNode.

first-contributions

🚀✨ Help beginners to contribute to open source projects

github-slideshow

A robot powered training repository :robot:

hdl-tools

Facilitates building open source tools for working with hardware description languages (HDLs)

hello-world

Testing

helloworld

My first repository

hugo-ink

Crisp, minimal personal website and blog theme for Hugo

i2c

Verilog HDL I2C implementation

ip-expander

Expands ranges of ip given in input .csv file and creates a output .text file.

jobeval

This is the program to create Job Evaluation Reports

judgement-python

Python

larbs

Luke's Auto-Rice Bootstrapping Scripts: Installation Scripts for My Arch Linux Meta-Distribution

legion-y540_brightness_fix

myappsample

Sample app

next_word_prediction

Using transformers to predict next word and predict <mask> word

pdfmerger

picorv32

PicoRV32 - A Size-Optimized RISC-V CPU

playingcards

Playing Cards - Judgement

printf-tac-toe

tic-tac-toe in a single call to printf