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Name: Dustin Richmond
Type: User
Company: University of California, Santa Cruz
Bio: Building Secure, Usable, (Hardware) Systems since 1989.
Location: Santa Cruz
Blog: www.dustinrichmond.com
Name: Dustin Richmond
Type: User
Company: University of California, Santa Cruz
Bio: Building Secure, Usable, (Hardware) Systems since 1989.
Location: Santa Cruz
Blog: www.dustinrichmond.com
Official repository of the AWS EC2 FPGA Hardware and Software Development Kit
PYNQ Hackathon 2017 Challenge 2
DRAMsim3: a Cycle-accurate, Thermal-Capable DRAM Simulator
Synthesizable Higher-Order Functions (Patterns) for C++
RISC-V by VectorBlox
RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)
Python Productivity for ZYNQ
General Repository for PYNQ Hackathon Resources
A Tutorial on Putting High-Level Synthesis cores in PYNQ
Networking Overlay on PYNQ
A short tutorial on how to install ZeroTier on PYNQ (2.3+)
Package for producing Gradescope-compatible results.json files with Pytest tests
A Python library for communicating with Arduino microcontroller boards
source code to readthedocs.org
The RIFFA development repository
RISC-V Integration for PYNQ
Rocket Chip Generator
RISC-V CPU Core
the Sampa group website
Shielded Enclaves for Cloud FPGAs
Verilator open-source SystemVerilog simulator and lint system
A FPGA friendly 32 bit RISC-V CPU implementation
Read-only mirror of Wireshark's Git repository. GitHub won't let us disable pull requests. ☞ THEY WILL BE IGNORED HERE ☜ Please upload them at https://code.wireshark.org/review/ .
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A server is a program made to process requests and deliver data to clients.
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Some thing interesting about visualization, use data art
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Open source projects and samples from Microsoft.
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Data-Driven Documents codes.
China tencent open source team.