Comments (7)
doonny
commented on August 25, 2024
Could you run sw emulation ?
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lloo099
commented on August 25, 2024
@Alsumbjip Hi, do u deploy PipeCNN successfully in U200? I am also want to try it. thanks,
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lloo099
commented on August 25, 2024
Hi Prof. Dong, @doonny I also try to deploy your NN on U200. sw_emu is well implement on U200 platform. But hw and hw_emu are failed, you may check below information:
(I just modify platform to U200 in makefile, and doesn't change config which means it use U50 config for my U200. As I don't know how to define ur config file for U200, and could you help me with that? Many thanks!)
INFO: [v++ 60-1306] Additional information associated with this v++ link can be found at:
Reports: /home/enai/Desktop/project/enai0/PipeCNN/project_xilinx/build.hw_emu/reports/link
Log files: /home/enai/Desktop/project/enai0/PipeCNN/project_xilinx/build.hw_emu/logs/link
INFO: [v++ 60-1657] Initializing dispatch client.
Running Dispatch Server on port:45307
INFO: [v++ 60-1548] Creating build summary session with primary output /home/enai/Desktop/project/enai0/PipeCNN/project_xilinx/build.hw_emu/conv.xclbin.link_summary, at Wed Nov 24 22:11:00 2021
INFO: [v++ 60-1316] Initiating connection to rulecheck server, at Wed Nov 24 22:11:00 2021
Running Rule Check Server on port:46179
INFO: [v++ 60-1315] Creating rulecheck session with output '/home/enai/Desktop/project/enai0/PipeCNN/project_xilinx/build.hw_emu/reports/link/v++_link_conv_guidance.html', at Wed Nov 24 22:11:01 2021
INFO: [v++ 60-895] Target platform: /tools/Xilinx/Vitis/2020.1/platforms/xilinx_u200_xdma_201830_2/xilinx_u200_xdma_201830_2.xpfm
INFO: [v++ 60-1578] This platform contains Device Support Archive '/tools/Xilinx/Vitis/2020.1/platforms/xilinx_u200_xdma_201830_2/hw/xilinx_u200_xdma_201830_2.dsa'
INFO: [v++ 60-1302] Platform 'xilinx_u200_xdma_201830_2.xpfm' has been explicitly enabled for this release.
INFO: [v++ 60-629] Linking for hardware emulation target
INFO: [v++ 60-423] Target device: xilinx_u200_xdma_201830_2
WARNING: [v++ 60-889] User-specified kernel frequency for ID 0 is the same as the default frequency 300 MHz, so it will be ignored
INFO: [v++ 60-1332] Run 'run_link' status: Not started
INFO: [v++ 60-1443] [22:11:08] Run run_link: Step system_link: Started
INFO: [v++ 60-1453] Command Line: system_link --xo /home/enai/Desktop/project/enai0/PipeCNN/project_xilinx/tmp.hw_emu/memRead.xo --xo /home/enai/Desktop/project/enai0/PipeCNN/project_xilinx/tmp.hw_emu/coreConv.xo --xo /home/enai/Desktop/project/enai0/PipeCNN/project_xilinx/tmp.hw_emu/memWrite.xo --xo /home/enai/Desktop/project/enai0/PipeCNN/project_xilinx/tmp.hw_emu/maxPool.xo -keep --config /home/enai/Desktop/project/enai0/PipeCNN/project_xilinx/build.hw_emu/link/int/syslinkConfig.ini --xpfm /tools/Xilinx/Vitis/2020.1/platforms/xilinx_u200_xdma_201830_2/xilinx_u200_xdma_201830_2.xpfm --target emu --output_dir /home/enai/Desktop/project/enai0/PipeCNN/project_xilinx/build.hw_emu/link/int --temp_dir /home/enai/Desktop/project/enai0/PipeCNN/project_xilinx/build.hw_emu/link/sys_link
INFO: [v++ 60-1454] Run Directory: /home/enai/Desktop/project/enai0/PipeCNN/project_xilinx/build.hw_emu/link/run_link
INFO: [SYSTEM_LINK 60-1316] Initiating connection to rulecheck server, at Wed Nov 24 22:11:09 2021
INFO: [SYSTEM_LINK 82-70] Extracting xo v3 file /home/enai/Desktop/project/enai0/PipeCNN/project_xilinx/tmp.hw_emu/memRead.xo
INFO: [SYSTEM_LINK 82-70] Extracting xo v3 file /home/enai/Desktop/project/enai0/PipeCNN/project_xilinx/tmp.hw_emu/coreConv.xo
INFO: [SYSTEM_LINK 82-70] Extracting xo v3 file /home/enai/Desktop/project/enai0/PipeCNN/project_xilinx/tmp.hw_emu/memWrite.xo
INFO: [SYSTEM_LINK 82-70] Extracting xo v3 file /home/enai/Desktop/project/enai0/PipeCNN/project_xilinx/tmp.hw_emu/maxPool.xo
INFO: [SYSTEM_LINK 82-53] Creating IP database /home/enai/Desktop/project/enai0/PipeCNN/project_xilinx/build.hw_emu/link/sys_link/_sysl/.cdb/xd_ip_db.xml
INFO: [SYSTEM_LINK 82-38] [22:11:09] build_xd_ip_db started: /tools/Xilinx/Vitis/2020.1/bin/build_xd_ip_db -ip_search 0 -sds-pf /home/enai/Desktop/project/enai0/PipeCNN/project_xilinx/build.hw_emu/link/sys_link/emu/xilinx_u200_xdma_201830_2_emu.hpfm -clkid 0 -ip /home/enai/Desktop/project/enai0/PipeCNN/project_xilinx/build.hw_emu/link/sys_link/iprepo/xilinx_com_hls_memRead_1_0,memRead -ip /home/enai/Desktop/project/enai0/PipeCNN/project_xilinx/build.hw_emu/link/sys_link/iprepo/xilinx_com_hls_maxPool_1_0,maxPool -ip /home/enai/Desktop/project/enai0/PipeCNN/project_xilinx/build.hw_emu/link/sys_link/iprepo/xilinx_com_hls_memWrite_1_0,memWrite -ip /home/enai/Desktop/project/enai0/PipeCNN/project_xilinx/build.hw_emu/link/sys_link/iprepo/xilinx_com_hls_coreConv_1_0,coreConv -o /home/enai/Desktop/project/enai0/PipeCNN/project_xilinx/build.hw_emu/link/sys_link/_sysl/.cdb/xd_ip_db.xml
INFO: [SYSTEM_LINK 82-37] [22:11:11] build_xd_ip_db finished successfully
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1439.266 ; gain = 0.000 ; free physical = 9123 ; free virtual = 19872
INFO: [SYSTEM_LINK 82-51] Create system connectivity graph
INFO: [SYSTEM_LINK 82-102] Applying explicit connections to the system connectivity graph: /home/enai/Desktop/project/enai0/PipeCNN/project_xilinx/build.hw_emu/link/sys_link/cfgraph/cfgen_cfgraph.xml
INFO: [SYSTEM_LINK 82-38] [22:11:11] cfgen started: /tools/Xilinx/Vitis/2020.1/bin/cfgen -sc memRead_1.bias_out:coreConv_1.bias_in -sc memRead_1.weight_out:coreConv_1.weight_in -sc memRead_1.data_out:coreConv_1.data_in -sc coreConv_1.conv_out:batchNorm_1.conv_in -sc coreConv_1.bypass_out:memWrite_1.bypass_in -sc batchNorm_1.bn_out:memWrite_1.bn_in -dmclkid 0 -r /home/enai/Desktop/project/enai0/PipeCNN/project_xilinx/build.hw_emu/link/sys_link/_sysl/.cdb/xd_ip_db.xml -o /home/enai/Desktop/project/enai0/PipeCNN/project_xilinx/build.hw_emu/link/sys_link/cfgraph/cfgen_cfgraph.xml
INFO: [CFGEN 83-0] Kernel Specs:
INFO: [CFGEN 83-0] kernel: coreConv, num: 1 {coreConv_1}
INFO: [CFGEN 83-0] kernel: maxPool, num: 1 {maxPool_1}
INFO: [CFGEN 83-0] kernel: memRead, num: 1 {memRead_1}
INFO: [CFGEN 83-0] kernel: memWrite, num: 1 {memWrite_1}
INFO: [CFGEN 83-0] Stream Specs:
INFO: [CFGEN 83-0] memRead_1.bias_out => coreConv_1.bias_in
INFO: [CFGEN 83-0] memRead_1.weight_out => coreConv_1.weight_in
INFO: [CFGEN 83-0] memRead_1.data_out => coreConv_1.data_in
INFO: [CFGEN 83-0] coreConv_1.conv_out => batchNorm_1.conv_in
INFO: [CFGEN 83-0] coreConv_1.bypass_out => memWrite_1.bypass_in
INFO: [CFGEN 83-0] batchNorm_1.bn_out => memWrite_1.bn_in
ERROR: [CFGEN 83-2291] --sc tag applied with invalid slave kernel instance: batchNorm_1
ERROR: [CFGEN 83-2284] --sc tag applied to nonexistant port coreConv_1.bypass_out
ERROR: [CFGEN 83-2284] --sc tag applied to nonexistant port memWrite_1.bypass_in
ERROR: [CFGEN 83-2291] --sc tag applied with invalid master kernel instance: batchNorm_1
ERROR: [CFGEN 83-2284] --sc tag applied to nonexistant port memWrite_1.bn_in
ERROR: [CFGEN 83-2298] Exiting due to previous error
ERROR: [SYSTEM_LINK 82-36] [22:11:13] cfgen failed
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1439.266 ; gain = 0.000 ; free physical = 9123 ; free virtual = 19871
ERROR: [SYSTEM_LINK 82-62] Error generating design file for /home/enai/Desktop/project/enai0/PipeCNN/project_xilinx/build.hw_emu/link/sys_link/cfgraph/cfgen_cfgraph.xml, command: /tools/Xilinx/Vitis/2020.1/bin/cfgen -sc memRead_1.bias_out:coreConv_1.bias_in -sc memRead_1.weight_out:coreConv_1.weight_in -sc memRead_1.data_out:coreConv_1.data_in -sc coreConv_1.conv_out:batchNorm_1.conv_in -sc coreConv_1.bypass_out:memWrite_1.bypass_in -sc batchNorm_1.bn_out:memWrite_1.bn_in -dmclkid 0 -r /home/enai/Desktop/project/enai0/PipeCNN/project_xilinx/build.hw_emu/link/sys_link/_sysl/.cdb/xd_ip_db.xml -o /home/enai/Desktop/project/enai0/PipeCNN/project_xilinx/build.hw_emu/link/sys_link/cfgraph/cfgen_cfgraph.xml
ERROR: [SYSTEM_LINK 82-96] Error applying explicit connections to the system connectivity graph
ERROR: [SYSTEM_LINK 82-79] Unable to create system connectivity graph
INFO: [v++ 60-1442] [22:11:13] Run run_link: Step system_link: Failed
Time (s): cpu = 00:00:06 ; elapsed = 00:00:05 . Memory (MB): peak = 1346.410 ; gain = 0.000 ; free physical = 9149 ; free virtual = 19897
ERROR: [v++ 60-661] v++ link run 'run_link' failed
ERROR: [v++ 60-626] Kernel link failed to complete
ERROR: [v++ 60-703] Failed to finish linking
INFO: [v++ 60-1653] Closing dispatch client.
Could you run sw emulation ?
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lloo099
commented on August 25, 2024
Update on U200: just compiled VGG-16 on U200 successfully. But haven't tried ResNet. Pls tell me if anyone run ResNet on U200. Thanks,
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zyt1024
commented on August 25, 2024
Hello,If I run on the u200, my config_sp.u200 file was copied from config_sp.u50. What needs to be modified? I don't know how to modify the config_sp.u200 file, and could you help me with that? Many thanks!
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zyt1024
commented on August 25, 2024
Update on U200: just compiled VGG-16 on U200 successfully. But haven't tried ResNet. Pls tell me if anyone run ResNet on U200. Thanks,
Hello,If I run on the u200, my config_sp.u200 file was copied from config_sp.u50. What needs to be modified? I don't know how to modify the config_sp.u200 file, and could you help me with that? Many thanks!
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zyt1024
commented on August 25, 2024
Update on U200: just compiled VGG-16 on U200 successfully. But haven't tried ResNet. Pls tell me if anyone run ResNet on U200. Thanks,
Hello, I also runnedVGG-16 on U200 successfully. but the performance on the U200 is not very good. How about your performance? this is my.
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Related Issues (20)
- How can i run this project in ZCU102 with SD card? HOT 3
- data_test1.dat file
- In YOLO
- How to fix Wrong Results with Board De1Soc HOT 2
- Need information about your project ! HOT 1
- How to caculate Coefficients lookup table for lrn computation
- make fpga error for xilinx HOT 14
- How to debug from the code. HOT 1
- Unable to download Data set HOT 2
- Integrate the similar module mult_add_fix8bx4 into the system. HOT 1
- Possibility of running on 3rd party board HOT 1
- Software emulation OpenCL runtime error, Xilinx/Vitis HOT 2
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- Make host error, no opencl header files, ZCU102/Vitis/Xilinx HOT 5
- project_xilinx HardWare on U200 get a poor performance
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