Comments (1)
The generated assembly code of different implementations
Compiler: ARM64 GCC 11.1
Optimization: -O2
ARM32 with unzip vector intrinsic:
https://godbolt.org/z/rhdcP7Khe
ARM64 with unzip vector intrinsic:
https://godbolt.org/z/ehvn51To3
Extract narrow and shift implementation:
https://godbolt.org/z/7Ybof1Y1K
The unzip vector implementation has less assembly code.
from sse2neon.
Related Issues (20)
- `_mm_aesimc_si128` is absent HOT 1
- Relaxed type casting HOT 2
- Errors when compiling with gcc for M1 HOT 2
- Generate more random test inputs HOT 2
- Cover complete immediate numbers in tests
- Optimize _mm_round_pd within 2^52 only HOT 2
- platform aarch64, cannot initialize paramter of float32x4_t with __m128d HOT 2
- Typo in sse2neon.h line 8029 HOT 5
- gcc sanitizer fails on _mm_loadu_si128 HOT 4
- _mm_dp_ps does not always match x86_64 HOT 1
- "warning: left shift count >= width of type" in test suite HOT 5
- Clang optimizing SSE2NEON_PRECISE_MINMAX incorrectly HOT 2
- error when I compile in Nvidia Orin HOT 3
- error: βvrndiq_f32β was not declared in this scope HOT 3
- New version/release HOT 2
- `_mm_shuffle_epi8` bit 7 of idx is not meaningless HOT 3
- Error compiling with GCC 8.3.0 HOT 7
- Optimize CRC intrinisics for targets lacking of CRC extension
- Windows ARM64 Github actions HOT 1
- Get error "Unsupported target. Must be either ARMv7-A+NEON or ARMv8-A." on armv7 system HOT 2
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