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16bit-risc-processor

16bit RISC Processor Verilog

8-bits-risc-cpu-verilog

Architecture and Verilog Implementation of 8-bits RISC CPU based on FSM. 基于有限状态机的8位RISC（精简指令集）CPU（**处理器）简单结构和Verilog实现。

axi_bfm

AXI4 BFM in Verilog

basic-simd-processor-verilog-tutorial

Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clock cycle will be used to load values into the registers. The second will be for performing the operations. 6-bit opcodes are used to select the functions. The instruction code, including the opcode, will be 18-bit.

community

一个仿照牛客网实现的讨论社区，不仅实现了基本的注册，登录，发帖，评论，点赞，回复功能，同时使用前缀树实现敏感词过滤，使用wkhtmltopdf生成长图和pdf，实现网站UV和DAU统计，并将用户头像等信息存于七牛云服务器。

convolutional-neural-network

Implementation of CNN using Verilog

core_ddr3_controller

A DDR3 memory controller in Verilog for various FPGAs

eladmin

项目基于 Spring Boot 2.1.0 、 Jpa、 Spring Security、redis、Vue的前后端分离的后台管理系统，项目采用分模块开发方式， 权限控制采用 RBAC，支持数据字典与数据权限管理，支持一键生成前后端代码，支持动态路由

ethernet-design-verilog

Gigabit Ethernet UDP communication driver

ghostnet.pytorch

[CVPR2020] GhostNet: More Features from Cheap Operations

lanlaninterview

此仓库将包含各大银行的基本介绍，笔试面试特点，发现这个宝库就离上岸不远了，哼

miaosha

Spring Boot+MyBatis-Plus+Redis+RabbitMQ高并发商品秒杀系统后端代码（前后端分离项目，单体架构版本）

miaosha-web

高并发商品秒杀系统前端代码（前后端分离项目）

mriscv

A 32-bit Microcontroller featuring a RISC-V core

rethinking_bottleneck_design

risc-processor

32-bit RISC processor

risc-v

A simple RISC-V CPU written in Verilog.

risc-v-32i

体系结构课程实验：RISC-V 32I 流水线 CPU，实现37条指令，转发，冒险检测，Cache，分支预测器

risc-v-cpu

简易 risc-v 处理器设计

riskow

Learning how to make a RISC-V

shufflenet

ShuffleNet in PyTorch. Based on https://arxiv.org/abs/1707.01083

skipnet

Code for SkipNet: Learning Dynamic Routing in Convolutional Networks (ECCV 2018)

story-admin

Springboot+Shiro+jwt+Redis+Mybatis 有效期内Token刷新方案

system-bus-design-verilog

This is a Multi master Multi slave compatible system bus design modeled using verilog. This is much like AMBA AHB Specification

tinyriscv

A very simple and easy to understand RISC-V core.

ucas-covid19

ucas疫情防控每日填报助手

verilog-uart

Verilog UART

vueblog

一个前后端分离的简单博客案例，适合刚入门vue，学前后端分离的童鞋！

xiaomi

基于Vue + SpringBoot实现的前后端分离的仿小米商城项目，包含秒杀模块。