TX/RX Routine failing after first full buffer transfer about jcap HOT 15 CLOSED

Ok @konimaru tell me something: should changing a dira bit to 0 (input) not cause that pin to be high impedance or floating, and therefor pulled low when there's a pull-down resistor on that pin?

Because I just uncovered a major source of the issue in the fact that performing:

or      outa, TxPin
or      dira, TxPin
andn    dira, TxPin

results in TxPin remaining high unless an andn is performed on outa and another dira toggle is performed.

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Satisfied by commit 0e2d445

The problem appears to have been the fact that toggling dira does not result in a toggle of the output itself, even with pull-down resistors: the pin is still actively driven.

This behavior wasn't easy to catch before because it appears it's non-deterministic, and when debugging the ACK signalling here its behavior was nominal.

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Driving a dira bit low gives you a floating (input) pin independent of the outa state. IOW the connected wire will be either left floating or pulled up/down.

Some of the I2C drivers work like this (i.e. they depend on external pull-ups to do the work) as does the (in)famous FullDuplexSerial object (if configured to do so).

So this looks to me like an FPGA issue perhaps?

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@konimaru my entire project is now running on 100% actual hardware: two P8X32As w/ support circuitry et. EEPROMs. I'm using a 10K pull down resistor on the data line. Does this sounds like a fault in the uC IC then? Because I "fixed" the problem with explicit outa instructions.

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Let me try this at home. How long is your cable?

Can you easily change pins?

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@konimaru cable is a few inches; the two uCs are on the same standard breadboard (breadboards being notorious for signal noise and ground plane sinking, maybe a source of the problem itself?)

Pins are easily changed in both TX and RX: TX by changing the variable in the vga_tx CON section, and RX by changing the variable at the bottom of the vga_rx PASM section. I should probably standardize that, eh?

I've tried changing pins during debugging to no avail.

I don't say it enough but thanks again for lending your time, effort and experience to my little hobby project :)

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So effectively the sequence (plus pull-down)

or      outa, TxPin
or      dira, TxPin
andn    dira, TxPin

is all I need to see if it works or not?

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@konimaru yep that should be the most trivial case

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Just occurred to me that the behaviour your described would suggest that the pull-down isn't connected. IOW you can pull the pin up/down and then it stays there (even though it's floating).

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@konimaru I completely agree! I can do a sanity check when I get home, but I'm 99.9% certain one end of a 10K resistor is attached to pin 0, and the other end is attached to ground. Maybe I'm getting some strange impedence effect, and I need to lower the pull down resistor value?

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Just checked on my trusty demoboard with a 10K pulldown. One cog just samples a pin (3) and copies its state to an LED pin (23). With the sequence in question (even in Spin) it stays high after the pin is set floating (no pulldown) for a while. With the pulldown in place I never see a blip on the LED.

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At PASM level I get an expected 4 cycles with forced outa toggling. Switching off dira instead clocks in with 23 cycles (10K pull-down). So maybe the 10K are a bit high for this purpose.

CON
  _clkmode = XTAL1|PLL16X
  _xinfreq = 5_000_000

CON
  PIN = 3
  
VAR
  long  stack[32]
  
PUB null

  cognew(@main, 0)
  cognew(link, @stack{0})
{
  waitcnt(clkfreq + cnt)
  
  outa[PIN] := 1
  dira[PIN] := 0
} 
  waitpne(0, 0, 0)

PRI link

  ctra := constant(%0_11010_000 << 23 | PIN)            ' LOGIC A
  frqa := 1
  
  waitpeq(%1000, %1000, 0)
  waitpne(%1000, %1000, 0)
  
  dira[23..16]~~
  outa[23..16] := phsa <# 255

  waitpne(0, 0, 0)
  
DAT             org     0

main            or      dira, #|< PIN

                rdlong  cnt, #0
                add     cnt, cnt
                waitcnt cnt, #0

                or      outa, main
'               mov     outa, #0                        '  4 cycles
                mov     dira, #0                        ' 23 cycles (10K pull-down)

                waitpeq $, #0

                fit
                
DAT

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@konimaru Interesting; I was under the impression that 10K was standard across the board as a pull-down value for P8X pins. I'm thinking this may also be the cause of issue #49. Thanks for the legwork!

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I'd leave the pull-down in (just to have a base line) and do a forced outa.

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@konimaru scratch all of that I'm picking up what you're putting down now. So the time constant for the circuit created by the interconnected prop is defined by a 20 pF mutual capacitance. Just based on the 23 sysclock count you identified, I need to drop the resistor down to 1K (minimum of 1.4 to be precise).

Regardless, I'm going to keep the explicit driver instructions because a digital margin of error is better than an analogue margin of error.

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