classiccomputers Goto Github PK

apb_uart_sv

arduino_freertos

FreeRtos tutorial examples on arduino

bgnet

Beej's Guide to Network Programming source

bookworm

A simple ebook reader for Elementary OS

chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

chisel-bootcamp

Generator Bootcamp Material: Learn Chisel the Right Way

chisel-template

A template project for beginning new Chisel work

chiselverify

A dynamic verification library for Chisel.

compose

Define and run multi-container applications with Docker

courses-introduction-to-python

Introduction to Python by Filip Schouwenaars

dirv

This is my first trial project for designing RISC-V in Chisel

ebaz4205

A 5$ Xilinx ZYNQ development board.

emba

emba - An analyzer for Linux-based firmware of embedded devices.

fpga_designs

FPGA design repository

free-devops-books-1

A curated collection of free DevOps related eBooks

huffman-encoding-verilog

Huffman encoding in Verilog Hardware Definition Language.

iacc-riscv

An Incremental Approach to Compiler Construction for RISC-V

introductory-guide-to-chisel

「Chiselを始めたい人に読んで欲しい本」のサンプルコード用リポジトリ

jpeg_compression

Hardware Implementation of DCT-based JPEG compression in Verilog.

jupyter-scala

Lightweight Scala kernel for Jupyter / IPython 3

kicad-source-mirror

This is an active mirror of the KiCad development branch, which is hosted at GitLab (updated every time something is pushed). Pull requests on GitHub are not accepted or watched.

latex-examples

An example assignment in LaTeX.

linux

Linux kernel source tree

linux-device-driver-development-cookbook

Linux Device Driver Development Cookbook, published by Packt

llvm-11-tutorials

A blog for LLVM(v11.0.0) beginner, step by step, with detailed documents and comments. Record the way I learn LLVM.

markdownviewerplusplus

A Notepad++ Plugin to view a Markdown file rendered on-the-fly

mips-pipeline-processor

A pipelined implementation of the MIPS processor featuring hazard detection as well as forwarding

mips-processor-8bit

8-bit processor in Verilog Hardware Definition Language. The architecture is MIPS (Microprocessor without Interlocked Pipeline Stages).

openlane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

project-template

A fork that translates and explains the templates of the RISC-V Project