Interrupt issue with the test application about zynq-xdma HOT 5 CLOSED

The zynq-xdma project is not being actively updated by me. I'll accept any patches or fixes but the rapid change of Xilinx code changes got too much for me to keep up with.

I have an alternative project that replaced the Xilinx DMA Engine, kernel driver etc:

https://github.com/bmartini/zynq-axis

The zynq-aixs project does everything that the zynq-xdma project does but is also easier to control from the FPGA. When I replaced all the xdma to axis in my projects I was able to get a reduced resource utilization and a better speed.

If you do fine a solution to your problem feel, free to send me the patch and I'll pull.

from zynq-xdma.

Thank you for the prompt response. I am presently going through the zynq-axis, I see that you have made your custom logic and interfaced it to the S_AXI_HP bus . I am presently using the AXI DMA IP. Any pointers in regards of using the zynq-axis with AXI DMA IP will be greatly appreciated. I could understand mapping of the configuration registers using the UIO framework, however I could not understand the mapping of MM2S and S2MM channels (wrt to the address map of the vivado hardware project)

As soon as I am able to debug the DMA engine wrapper code I will post it.

Thank you in advance.

from zynq-xdma.

I checked the devicetree/bindings/dma/xilinx documentation and commented out the following line

interrupts = <0 30 4>, <0 29 4>;

the irqpoll error vanished. Now I am getting this output

<xdma> init: registered
<xdma> probe: number of devices found: 1
random: nonblocking pool is initialized
<xdma> file: open()
<xdma> ioctl: XDMA_TEST_TRANSFER
<xdma> test: rx buffer before transmit:
Y   Y   Y   Y   Y   Y   Y   Y   Y   Y
<xdma> test: xdma_start_transfer rx
<xdma> test: xdma_start_transfer tx
<xdma> test: time to prepare DMA channels [us]: 29
<xdma> Error: transfer timed out
<xdma> test: DMA transfer time [us]: -3405
<xdma> test: DMA bytes sent: 1024
<xdma> test: DMA speed in Mbytes/s: 0
<xdma> test: rx buffer after transmit:
Y   Y   Y   Y   Y   Y   Y   Y   Y   Y
<xdma> file: close()
root@linaro-ubuntu-desktop:~# /build/zynq-xdma/demo/app
test: dst buffer before transmit:
A   A   A   A   A   A   A   A   A   A
test: dst buffer after transmit:
A   A   A   A   A   A   A   A   A   A
root@linaro-ubuntu-desktop:~# /build/zynq-xdma/demo/
.Xil/      .settings/ app        demo       test       
root@linaro-ubuntu-desktop:~# /build/zynq-xdma/demo/demo 
test: rx buffer before transmit:
C   C   C   C   C   C   C   C   C   C
Number of devices: 1
devices tx chan: 7e0bb8b4, tx cmp:7e145080, rx chan: 7e0bb7f4, rx cmp: 7e145100
config rx chans
config tx chans
config rx buffer
config tx buffer
config rx trans
config tx trans
test: rx buffer after transmit:
C   C   C   C   C   C   C   C   C   C

I am unable to transfer the data. I am checking for bugs. Will the difference between address range/map in Vivado and the driver cause this problem? Will keep you posted though.
Thank you in advance.

from zynq-xdma.

Your code is working fine for Direct DMA. I had limited the addresses mapping in the Vivado to just 4MB for the AXI DMA. I guess the DMA engine was using some other base address, and hence the Address Decode Error as

xilinx-dma 40400000.dma: Channel 8dfe8590 has errors 41, cdr 0 tdr 0

After changing the address map in Vivado to cover the whole 1GB, the error is no longer present. One curious question though, If I wish to restrict the physical address used by the dmaengine/axidma driver, how do you go about it?
Thank you for your help and sharing great piece of code.

from zynq-xdma.

Hi Kildeepj and bmartini,

I encounter the same Error as belows:
xilinx-vdma 40400000.dma: Channel 8dfe8590 has errors 41, cdr 0 tdr 0

I have tried your solutions to change the address map in Vivado to 1GB. But the issue still there.

Do you have any idea?

from zynq-xdma.