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Biren Parmar's Projects

design-and-implementation-of-a-cruise-control-system icon design-and-implementation-of-a-cruise-control-system

- Designed RTL of cruise control system in Verilog and verified the design using Verilog testbench. - Synthesized the design using Design Vision and performed pre-layout Static Timing Analysis on the design using Synopsys Primetime. - Performed automatic place and route on the generated netlist using SoC Encounter.

design-and-implementation-of-the-low-pass-digital-filter icon design-and-implementation-of-the-low-pass-digital-filter

- Implemented 6th order low-pass digital filter for a speech signal sampled at 44KHz in Matlab FDA tool. - Created quantized RTL(second order filter instanciated thrice) in Verilog with the coefficients represented with 12 bits and maintained SNR of 36.89. - Analyzed the correlation of the Verilog implementation against the Matlab filter implementation by a self-checking script that compared the output of the Verilog implementation versus the Matlab output of the quantized filter and found the error to be 0%.

design-and-verification-of-ldpc-decoder icon design-and-verification-of-ldpc-decoder

- Designed the LDPC decoder in the Matlab using the min-sum approach. - Designed quantized RTL in Verilog with the min-sum approach and parallel architecture. - Created modules for all variants of the variable node unit(VNU) and the check-node unit(CNU) based on the H matrix. Created script for module instantiation of VNU and CNU as per the H matrix. - Verified the functionality of the Verilog implementation by self-checking test-bench in Verilog to compare the results with Matlab.

improving-cache-performance-by-exploiting-read-write-disparity icon improving-cache-performance-by-exploiting-read-write-disparity

- Analysed the data criticality and locality, i.e. cache lines that read versus the cache lines that are only written and exploited the disparity between the read and the write criticality using the proposed Read Write Partitioning, to divide the LLC into two logical partitions for dirty and clean lines. - Implemented the Read Write Partitioning to predict the best partition sizes to increase the likelihood of the future read hits in Simple-Scalar 3.0 and analysed the results of benchmarks of the SPEC CPU2000 suite. - Attained performance improvement in terms of Miss rate reduction by 10% and memory traffic reduction by 20 %. - Compared RWP with the prior state of the art cache management policies and found that RWP outperforms all of them, apart from few outliers. The analysis of the outliers was also performed.

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